Intel® High Level Synthesis Compiler Pro Edition: User Guide

ID 683456
Date 12/13/2021
Public

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2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition

The Intel® High Level Synthesis (HLS) Compiler parses your design and compiles it to an x86-64 object or RTL code optimized for Intel® FPGA device families. It also creates an executable testbench. Use the x86-64 object to quickly test and debug the function of your design.

You can use the same testbench to verify your design both when it is compiled to x86-64 instructions or to RTL.

The Intel® HLS Compiler Pro Edition is command-line compatible with g++, and supports most of the g++ compiler flags. See the Intel® High Level Synthesis Compiler Reference Manual for a full list of compiler flags.

The Intel® HLS Compiler Pro Edition recognizes the same file name extensions as g++, namely .c, .C, .cc, .cpp, .CPP, .c++, .cp, and .cxx. The compiler treats all of these file types as C++. The compiler does not explicitly support C, other than as a subset of C++.

Important: The Intel® HLS Compiler Pro Edition treats all input files as C++17. The compiler does not support files conforming to newer C++ standards.
When you target the compilation to an FPGA, the Intel® HLS Compiler outputs an executable and a project directory. The default executable is a.out on Linux and a.exe on Windows. The default project directory is a.prj, and it contains the following outputs:
  • Generated IP
  • High-Level Design Reports (report.html)
  • Verification testbench files
  • Quartus project that you can use to accurately estimate area requirements and fMAX for your design.

To specify the name of the compiler output, include the -o <result> option in your i++ command, where <result> is the name of the executable. This command creates a project directory called <result>.prj.

Running the executable file runs your testbench. When you target the compilation to an x86-64 architecture, the output executable runs your design on the CPU like a regular C++ program. The output executable runs very quickly compared to running a simulation of your component RTL. When you target the compilation to an FPGA architecture, the output executable simulates your component RTL. This simulation can take a long time to run.

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