Intel® FPGA Power and Thermal Calculator User Guide

ID 683445
Date 6/26/2023
Public

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4.4. Intel® FPGA PTC - IP Wizard

The IP Wizard of the Intel® FPGA Power and Thermal Calculator (PTC) allows you to select, configure, and instantiate IP blocks which are then appended to your current design.
  1. You can launch the IP Wizard from the PTC File menu, by clicking File > IP Wizard or clicking the IP wizard button on the toolbar.
    Figure 24. Launching the IP Wizard
    Figure 25. Launching the IP Wizard with button
  2. The opening dialog box of the IP Wizard prompts you to select an IP from a pulldown list. Select the IP that you want to add to your design, and click Next.
    Figure 26. IP Selection Page
  3. The IP Wizard then displays a dialog box for configuring your selected IP. Enter the appropriate information, and click Next.
    Figure 27. IP Configuration PageThe IP Parameter Configuration page parameters depend on the IP you select. These parameters are a subset of the parameters in IP Catalog wizards. Refer to the appropriate IP User Guide for more details on each IP's parameters.
    Table 8.  IP Configuration FieldsThis table is only relevant for EMIF IPs in Intel Stratix 10 devices. .
    Column Heading Description
    Entity Name Specify a name for the entity.
    Hierarchy Node Specifies the name of the IP instance.
    Voltage Specifies the I/O voltage of the signaling between periphery device and interface.
    Data Width (Bits) Specifies the interface data width of the specific IP (in bits).
    Data Group Width Specifies the data group width.
    Memory Device(s) Specifies the number of memory devices connected to the interface.
    Total Address Width Specifies the total address width. This value is used to derive the total number of address pins required.
    DDR Rate Specifies the clock rate of user logic. Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200MHz.
    PHY Rate Specifies the clock rate of PHY logic. Determines the clock frequency of PHY logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that the PHY logic in the FPGA runs at 200MHz.
    Memory Clock Frequency (MHz) Specifies the frequency of memory clock (in MHz).
  4. The IP Wizard then displays the configuration details for your review. If you want to change any of the configuration, click Back. Otherwise, if you are satisfied with the configuration, click Finish.
    Figure 28. IP Configuration Review Page

After you exit the IP Wizard, the system appends new rows to the PTC pages (Logic, PLL, I/O, etc.), in accordance with the IP that you have added.