Intel® FPGA Power and Thermal Calculator User Guide

ID 683445
Date 6/26/2023
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4.2.2. Intel® FPGA PTC Hierarchy Manager

The Hierarchy Manager displays the dynamic power consumption for each hierarchy of the design, as entered in the Intel® FPGA Power and Thermal Calculator (PTC) data entry pages. The Hierarchy Manager allows you to enter and modify hierarchy names, import and export hierarchies, and delete unneeded hierarchy levels.

Figure 20.  Intel® FPGA PTC Hierarchy Manager


The Hierarchy Manager includes the following buttons and controls:

Table 7.  Hierarchy Manager Buttons and Controls
Button or Control Description
Rename Button Allows you to specify a new name for the currently selected design hierarchy.
Delete Button Allows you to delete the currently selected design hierarchy.
Export Button Allows you to export the currently selected hierarchy to a .ptc file. The exported .ptc can be imported into a higher level of the design, or shared with another designer. The .ptc includes all data relevant to the selected hierarchy and below. The exported .ptc file includes device selection settings, but does not include settings that are global to the design, such as thermal analysis settings. To save the complete design, including all global settings, use File > Save.
Import Button Allows you to import a previously generated Power and Thermal Calculator file, such as a .ptc file. The import appends the imported data to all existing sheets, as appropriate. To overwrite an existing design, use File > Open.
Note: If any imported global design settings conflict with the current design settings, the imported settings are ignored and an import warning message appears.
Duplicate command (right-click) Allows you to right-click a hierarchy and create a duplicate copy of the hierarchy.
Bulk Edit button Allows you to modify parameters of a specific hierarchical level and below if selected. All pages of the Intel® FPGA Power and Thermal Calculator reflect these changes.

For additional information, refer to Bulk Editing Hierarchies in the Intel FPGA PTC.