Intel® FPGA Power and Thermal Calculator User Guide

ID 683445
Date 3/31/2023

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3.4.1. Entering Hierarchy Information Into the Intel® FPGA PTC

If you want Intel® FPGA Power and Thermal Calculator (PTC) estimation to reflect your design hierarchy, you must first enter (or import from a prior PTC session) your design's power data and hierarchy level information into the Intel® FPGA PTC data entry pages. The Intel® FPGA PTC then reports, in watts, the subtotals of the power consumed by each architectural feature, for each level of design hierarchy.

When entering levels of hierarchy in the Intel® FPGA PTC, the pipe character (|) denotes a level of hierarchy. For example, the following notation indicates three levels of hierarchy. Hierarchy a is the highest level. Hierarchy b is the second level. Hierarchy c is the third level.


Instance paths may, optionally, begin with a leading pipe character (|). But regardless of whether a leading pipe is is there or not, paths are treated the same.

When you enter an entity name for a given hierarchy, the Intel® FPGA PTC automatically updates the entity name in the Hierarchy Manager and on all data-entry pages that include that hierarchy.

To enter design hierarchy information into the Intel® FPGA PTC, follow these steps:

  1. Open your version of the Intel® FPGA PTC, as Accessing the Intel FPGA Power and Thermal Calculators describes.
  2. Click the View menu and select one of the Intel® FPGA PTC pages, such as the Logic page.
    Figure 4.  Intel® FPGA PTC Logic Page

  3. In the Full Hierarchy Name cell, type the hierarchical name of a hierarchy in your design, using the pipe character (|) as the hierarchy level delimiter. For example, the following defines the b level of hierarchy that is child of hierarchy a:
    Figure 5. Entering Full Hierarchy Name in Intel® FPGA PTC

  4. In the Entity Name cell, enter the name of the design entity. If a newly entered hierarchy name already exists in the design, the Entity Name cell is already populated. Also, changing the entity name for a particular hierarchy name changes it for all_occurrences of that hierarchy name.
  5. Specify values for the #Half ALMs, #FFs, Clock Freq. (MHz), Toggle % and Routing Factor cells for each hierarchy. Repeat appropriate entries for design hierarchies on other pages.

    The instance appears hierarchically in the Hierarchy Manager in the Intel® FPGA PTC, showing the dynamic power estimate for each hierarchy level, and the cumulative power for all instances and hierarchy levels.

    Figure 6.  Intel® FPGA PTC Hierarchy Manager

  6. In the Hierarchy Manager, you can right-click any instance to Rename, Duplicate, or Export the Intel® FPGA PTC data for the levels of hierarchy that you define.