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5.10.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
The following three examples illustrate the Intel® FPGA PTC configuration for various E-tile channel PLL requirements.
Operation Mode | Data Rate | Digital/Analog Width | Power Mode | FEC | EHIP | Modulation | Digital Freq | # Refclks | Refclk Freq | VOD |
---|---|---|---|---|---|---|---|---|---|---|
Transmitter Only | 12800 | 16 | Normal Power | Bypass | Bypass | NRZ | 0 | 1 | 200 | 0 |
Operation Mode | Data Rate | Digital/Analog Width | Power Mode | FEC | EHIP | Modulation | Digital Freq | # Refclks | Refclk Freq | VOD |
---|---|---|---|---|---|---|---|---|---|---|
Transmitter Only | 8000 | 16 | Normal Power | Bypass | Bypass | NRZ | 0 | 1 | 125 | 0 |
Operation Mode | Data Rate | Digital/Analog Width | Power Mode | FEC | EHIP | Modulation | Digital Freq | # Refclks | Refclk Freq | VOD |
---|---|---|---|---|---|---|---|---|---|---|
Transmitter Only | 19660.8 | 40 | Normal Power | Bypass | Bypass | NRZ | 0 | 1 | 307 | 0 |
Alternatively, you can instantiate an E-Tile Transceiver-native PHY IP in PLL mode in your Intel® Quartus® Prime project, compile the project, and view the configuration in the Intel® FPGA PTC.