1.1.3. Relevant Features of the Cyclone V SoC Development Kit
The following list highlights the Cyclone® V SoC Development Kit components and features that are relevant to the Intel® FPGA SDK for OpenCL™ :
- Dual-core ARM® Cortex®-A9 CPU running 32-bit Linux.
- Advanced eXtensible Interface (AXI) bus between the HPS and the FPGA core fabric.
- Two hardened DDR memory controllers, each connecting to a 1 gigabyte (GB) DDR3 SDRAM.
- One DDR controller is accessible to the FPGA core only (that is, FPGA DDR).
- The other DDR controller is accessible to both the HPS and the FPGA (that is, HPS DDR). This shared controller allows free memory sharing between the CPU and the FPGA core.
- The CPU can reconfigure the FPGA core fabric.
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