Intel® FPGA SDK for OpenCL™: Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide

ID 683435
Date 11/06/2017
Public
Document Table of Contents

1.4. FPGA Reconfiguration

For SoC FPGAs, the CPU can reconfigure the FPGA core fabric without interrupting the CPU's operation. The FPGA Manager hardware block that straddles the HPS and the core FPGA performs the reconfiguration. The Linux kernel includes a driver that enables easy access to the FPGA Manager.
  • To view the status of the FPGA core, invoke the cat /sys/class/fpga/fpga0/status command.

The Intel® FPGA SDK for OpenCL™ program utility available with the Cyclone® V SoC Development Kit Reference Platform uses this interface to program the FPGA. When reprogramming an FPGA core with a running CPU, the program utility performs all of the following tasks:

  1. Prior to reprogramming, disable all communication bridges between the FPGA and the HPS, both H2F and LH2F bridges.

    Reenable these bridges after reprogramming completes.

    Attention: The OpenCL system does not use the FPGA-to-HPS (F2H) bridge. Refer to the HPS-FPGA Memory-Mapped Interfaces section in the Cyclone V Hard Processor System Technical Reference Manual for more information.
  2. Ensure that the link between the FPGA and the HPS DDR controller is disabled during reprogramming.
  3. Ensure that the FPGA interrupts on the FPGA are disabled during reprogramming. Also, notify the driver to reject any interrupts from the FPGA during reprogramming.

Consult the source code of the program utility for details on the actual implementation.

Warning:

Do not change the configuration of the HPS DDR controller when the CPU is running. Doing so might cause a fatal system error because you might change the DDR controller configuration when there are outstanding memory transactions from the CPU. This means that when the CPU is running, you may not reprogram the FPGA core with an image that uses HPS DDR in a different configuration.

Remember that the OpenCL system, and the Golden Hardware reference design available with the Intel® SoC FPGA Embedded Design Suite (EDS), sets the HPS DDR into a single 256-bit mode.

CPU system parts such as the branch predictor or the page table prefetcher might issue DDR commands even when it appears that nothing is running on the CPU. Therefore, boot time is the only safe time to set the HPS DDR controller configuration. This also implies that U-boot must have a raw binary file (.rbf) image to load into memory. Otherwise, you might be enabling the HPS DDR with unused ports on the FPGA and then potentially changing the port configurations afterwards. For this reason, the OpenCL Linux kernel driver no longer includes the logic necessary to set the HPS DDR controller configuration.

The SW3 dual in-line package (DIP) switches on the Cylone V SoC Development Kit control the expected form of the .rbf image (that is, whether the file is compressed and/or encrypted). C5soc, and the Golden Hardware Reference Design available with the SoC EDS, include compressed but unencrypted .rbf images. The SW3 DIP switch settings described in the Intel® FPGA SDK for OpenCL™ Cyclone V SoC Getting Started Guide match this .rbf image configuration.

Did you find the information on this page useful?

Characters remaining:

Feedback Message