Intel® FPGA SDK for OpenCL™: Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide

ID 683435
Date 11/06/2017
Public
Document Table of Contents

1.2. Porting the Reference Platform to Your SoC FPGA Board

To port the Cyclone® V SoC Development Kit Reference Platform to your SoC FPGA board, perform the following tasks:

  1. Select the one DDR memory or the two DDR memories version of the c5soc Reference Platform as the starting point of your design.
  2. Update the pin locations in the INTELFPGAOCLSDKROOT/board/c5soc/<board_variant>/top.qsf file,

    where INTELFPGAOCLSDKROOT is the path to the location of the Intel® FPGA SDK for OpenCL™ installation, and

    <board_variant> is the directory name of the board variant. The c5soc_sharedonly directory is for the board variant with one DDR memory system. The c5soc directory is for the board variant with two DDR memory systems.

  3. Update the DDR settings for the HPS and/or FPGA SDRAM blocks in the INTELFPGAOCLSDKROOT/board/c5soc/<board_variant>/system.qsys file.
  4. All Intel® FPGA SDK for OpenCL™ preferred board designs must achieve guaranteed timing closure. As such, the placement of the design must be timing clean. To port the c5soc board partition (acl_iface_partition.qxp) to your SoC FPGA board, perform the following tasks:
    For detailed instructions on modifying and preserving the board partition, refer to the Intel® Quartus® Prime Incremental Compilation for Hierarchical and Team-Based Design chapter of the Intel® Quartus® Prime Standard Edition Handbook.
    1. Remove the acl_iface_partition.qxp from the INTELFPGAOCLSDKROOT/board/c5soc/c5soc directory.
    2. Enable the acl_iface_region Logic Lock region by changing the Tcl command
      set_global_assignment -name LL_ENABLED OFF -section_id acl_iface_region

      to

      set_global_assignment -name LL_ENABLED ON -section_id acl_iface_region

    3. Compile an OpenCL kernel for your board.
    4. If necessary, adjust the size and location of the Logic Lock region.
    5. When you are satisfied that the placement of your design is timing clean, export that partition as the acl_iface_partition.qxp Intel® Quartus® Prime Exported Partition File.

      As described in the Establishing Guaranteed Timing Flow section of the A Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide, by importing this .qxp file into the top-level design, you fulfill the requirement of providing a board design with a guaranteed timing closure flow.

      For factors that might impact the quality of results (QoR) of your exported partition, refer to the General Quality of Results Considerations for the Exported Board Partition section in the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide.

    6. Disable the acl_iface_region Logic Lock region by reverting the command in Step 2 back to set_global_assignment -name LL_ENABLED OFF -section_id acl_iface_region.
  5. If your SoC FPGA board uses different pins and peripheries of the HPS block, regenerate the preloader and the device tree source (DTS) file. If you change the HPS DDR memory controller settings, regenerate the preloader.
  6. Create the SD flash card image.
  7. Create your Custom Platform, which includes the SD flash card image.
    Consider creating a runtime environment version of your Custom Platform for use with the Intel® FPGA Runtime Environment (RTE) for OpenCL. The RTE version of your Custom Platform does not include hardware directories and the SD flash card image. This Custom Platform loads onto the SoC FPGA system to allow host applications to run. In contrast, the SDK version of the Custom Platform is necessary for the SDK to compile OpenCL kernels.
    Tip: You may use the SDK version of your Custom Platform for the RTE. To save space, remove the SD flash card image from the RTE version of your Custom Platform.
  8. Test your Custom Platform.
    Refer to the Testing the Hardware Design section of the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide for more information.

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