Intel FPGA Programmable Acceleration Card N3000-N Data Sheet

ID 683434
Date 12/11/2020

2.2.6. Network Interface

The Intel® FPGA PAC N3000-N has two Quad Small Form-Factor Pluggable (QSFP) 28 cages on the faceplate panel.

25GbE network features:
  • 2 x 25 GbE per QSFP28
  • 4 X 25 GbE on QSFP A, QSFP B is disabled
  • Programmable Forward Error Correction (FEC) including Reed-Solomon Forward Error Correction (RS-FEC), BASE-R FEC (also known as Firecode) and no FEC
    Note: Support is provided for IEEE 802.3 clause 108 and clause 74. Clause 91 is not supported.
  • Supports 25GBASE-CR and 25GBASE-SR

The Intel® FPGA PAC N3000-N supports Short Reach (SR) optical transceivers and Direct Attached Copper (DAC) cables up to 3m in length. QSFP modules must consume no more than 3.5 watts. The table below lists Ethernet cables, QSFP modules and Ethernet switches known to work with the Intel® FPGA PAC N3000-N. Solution providers must validate Ethernet connectivity for the application.

Table 2.  QSFP28 Support for the Intel® FPGA PAC N3000-N using 25GbE Network Configuration
Module Manufacturer Part Number

QSFP28 Loopback Adapter Module, 100 Gb Ethernet, copper

Amphenol SF-100GLB3.5W-0DB

100GBASE-SR4 QSFP28 850nm 100m DOM Transceiver Module QSFP28-SR4-100G

12-Fibers MTP/MPO Female Type 1 OM4 50/125 Multimode Fiber Loopback Module LPM-OM4-12MTP
QSFP28-to-2xQSFP28 25 GbE copper breakout cable Mellanox

MCP7H00-G01AR (1.5m)

MCP7H00-G02AR (2.5m)

5m (16ft) MTP Female 12 Fibers Type B Plenum (OFNP) OM4 (OM3) 50/125 Multimode Elite Trunk Cable 68023
Ethernet Switch Cisco N9K-93180YC-FX
Ethernet Switch Mellanox MSN2410-CB2R
The Intel® FPGA PAC N3000-N is delivered with a sample FPGA workload that supports simple pass through functionality to demonstrate Ethernet functionality with the following capabilities:
  • User configurable pause frame flow control generation
  • User configurable maximum packet size up to 9600 bytes
  • Per port Ethernet statistics
The Intel® provided sample FPGA workload does not support the following:
  • Pausing of transmitted traffic in response to received pause frame
  • Auto-negotiation

You can create FPGA workloads that support these functions, if required.