Intel FPGA Programmable Acceleration Card N3000-N Data Sheet

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ID 683434
Date 12/11/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. System Compatibility 4. Mechanical Information 5. Thermal Specifications 6. Intel® Provided FPGA Image A. References B. Safety and Regulatory Information C. Document Revision History for the Intel FPGA Programmable Acceleration Card N3000-N Data Sheet
2. Overview x
2.1. Intel® FPGA PAC N3000-N Block Diagram 2.2. Overview of Product Features 2.3. PCIe Overview 2.4. Board Management Controller Overview
2.2. Overview of Product Features x
2.2.1. Intel® Arria® 10 GT FPGA 2.2.2. Intel® Ethernet Controller XL710-BM2 Network Interface Controller 2.2.3. On-Board Memory 2.2.4. Software and Firmware 2.2.5. Power 2.2.6. Network Interface
2.2.6. Network Interface x
2.2.6.1. Intel® Ethernet Connection C827 Retimer
2.4. Board Management Controller Overview x
2.4.1. Field Replaceable Unit Identification (FRUID) EEPROM
5. Thermal Specifications x
5.1. Cooling Requirements
B. Safety and Regulatory Information x
B.1. Regulatory Compliance
1. Introduction
2. Overview
3. System Compatibility
4. Mechanical Information
5. Thermal Specifications
6. Intel® Provided FPGA Image
A. References
B. Safety and Regulatory Information
C. Document Revision History for the Intel FPGA Programmable Acceleration Card N3000-N Data Sheet

2.2.1. Intel® Arria® 10 GT FPGA

The Intel® Arria® 10 FPGAs feature industry-leading programmable logic built on 20 nm process technology that integrates a rich feature set of embedded peripherals, embedded high-speed transceivers, hard memory controllers and IP protocol controllers. Variable-precision digital signal processing (DSP) blocks integrated with hardened floating point (IEEE 754-compliant) arithmetic blocks enable the Intel® Arria® 10 FPGAs to deliver floating point performance of up to 1.5 TFLOPS. Intel® Arria® 10 FPGAs have a comprehensive set of power-saving features. Combined, these features allow developers to build a versatile set of acceleration solutions.

Table 1.  Intel Arria 10 GT FPGA
Device Logic Elements (LE) Adaptive Logic Modules (ALMs) Registers M20K Memory Blocks M20K Memory (Mb) MLAB Memory (Mb) 18 x 19 Multipliers
GT 1150 1,150K 427,200 1,708K 2713 53 12.7 3036

When developing the accelerator function for the Intel® FPGA PAC N3000-N , select the 10AT115S1F45E1SG device.

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