Streaming DMA Accelerator Functional Unit User Guide: Intel FPGA Programmable Acceleration Card D5005

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ID 683424
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Streaming DMA AFU Description 3. Memory Map and Address Spaces 4. Software Programming Model 5. Running the AFU Example 6. Compiling the Accelerator Function (AF) 7. Simulating the AFU Example 8. Streaming DMA Accelerator Functional Unit User Guide Archive 9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. Streaming DMA AFU Description x
2.1. Hardware Subsystems 2.2. Streaming DMA Test System 2.3. Memory-to-Stream DMA BBB 2.4. Stream-to-Memory DMA BBB
3. Memory Map and Address Spaces x
3.1. Streaming DMA AFU Memory Map 3.2. Memory-to-Stream DMA BBB Memory Map 3.3. Stream-to-Memory DMA BBB Memory Map
5. Running the AFU Example x
5.1. Optimization for Improved DMA Performance
1. About this Document
2. Streaming DMA AFU Description
3. Memory Map and Address Spaces
4. Software Programming Model
5. Running the AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. Streaming DMA Accelerator Functional Unit User Guide Archive
9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide

5. Running the AFU Example

Before you begin:
  • Intel recommends you refer to the Quick Start Guide for your Intel® FPGA PAC D5005 to be familiar with running similar examples. Before you proceed through the following steps, verify that the OPAE_PLATFORM_ROOT environment variable is set to the OPAE SDK installation directory.
  • You must also set up two 1 GB hugepages to run the sample application using the instruction below: 
    sudo sh -c "echo 2 > /sys/kernel/mm/hugepages/hugepages-1048576kB\nr_hugepages"

Perform the following steps to download the Streaming DMA Accelerator Function (AF) bitstream, to build the application and driver, and to run the design example:

  1. Change to the Streaming DMA application and driver directory: 
    cd $OPAE_PLATFORM_ROOT/hw/samples/streaming_dma_afu/sw
  2. Build the driver and application: 
    make
  3. Download the streaming DMA AFU bitstream: 
    sudo fpgasupdate ../bin/streaming_dma_afu_unsigned.gbs
  4. Execute the host application to transfer 100 MB in 1 MB portions from host memory to the FPGA pattern checker: 
    ./fpga_dma_st_test -l off -s 104857600 -p 1048576 -r mtos -t fixed
  5. Execute the host application to transfer 100 MB in 1 MB portions from the FPGA pattern generator to host memory: 
    ./fpga_dma_st_test -l off -s 104857600 -p 1048576 -r stom -t fixed
  6. Execute the host application to transfer 100 MB in 1 MB portions from host memory back to host memory in loopback mode: 
    ./fpga_dma_st_test -l on -s 104857600 -p 1048576 -t fixed -f 0
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