3.2. Memory-to-Stream DMA BBB Memory Map
The M2S DMA BBB memory map provides the address offsets of all the locations within the BBB. The following streaming DMA AFU registers reside at offset 0x100 in the MMIO address space.
|Byte Address Offsets||Slave Name||Span in Bytes||Description|
|0x00||M2S DMA BBB DFH||0x40||Device feature header for the M2S DMA BBB. This DFH points to 0x100 as the next DFH offset.|
|0x40||M2S DMA Dispatcher CSR||0x20||
Control port for the M2S DMA Dispatcher CSR.The driver accesses this location to control the DMA or query its status.
|0x80||M2S DMA Descriptor Frontend CSR||0X40||Control port for the M2S DMA descriptor frontend. The driver accesses this location to control the descriptor frontend or query its status.|
Did you find the information on this page useful?