1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Intel HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6.2. Memory Operations
During flash memory access, the IP performs the following steps to allow you to perform any direct read or write operation:
- Write enable for write operation
- Check flag status register to make sure the operation has been completed at the flash
- Release waitrequest signal when operation completed
Memory operations are Avalon® memory-mapped operations. You must set the correct address on the address bus, write data if it is write transaction, drive burst count bus 1 if single transaction or desired burst count value and trigger the write or read signal.
Note: For multiple flash device setup, the address bus is extended to include the chip select value.
Figure 2. 8-Word Write Burst Waveform Example
Figure 3. 8-Word Reading Burst Waveform Example
Figure 4. 1-Byte Write byteenable = 4’b0001 Waveform Example
There are two internal unconstrained clocks in the Generic Flash Serial Interface Intel® FPGA IP core when you compile your design in the Intel® Quartus® Prime Pro Edition software. Intel® recommends that you constraint the path by using the following command:
create_generated_clock -name <name_of_generated_clock> -source [get_ports <input_clock_name>] -divide_by 2 [get_registers <path_of_the_unconstrained_path>]
Did you find the information on this page useful?