Generic Serial Flash Interface Intel® FPGA IP User Guide

ID 683419
Date 12/22/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.8.3. Flash Operations to Write Flash Registers

The following flash operations are used to write flash registers:

  • Write enhanced volatile configuration register
  • Write bank register
  • Write status register
  • Write configuration register
Note: You must execute the write enable operation before you start these operations.

The following registers are used to write the status of a register:

  • Flash command setting register
  • Flash command control register
  • Flash command write data 0 register

Perform the Write Status Register Operation to Protect Sector of Flash

proc write_status_register { } {
 global mp flash_cmd_setting flash_cmd_write_data_0 flash_cmd_ctrl
master_write_32 $mp $flash_cmd_setting 0x00001001
master_write_32 $mp $flash_cmd_write_data_0 0x0000007c
master_write_32 $mp $flash_cmd_ctrl 0x1

To perform the write status register operation, follow these steps:

  1. Define the global variables.
  2. Customize the write status register operation by writing to the flash command setting register.
    1. Set bit [7:0] of this register to 01 as 01h is the operation code of the write status register operation.
    2. Set bit [10:8] to 0 as this operation does not carry any address byte.
    3. Set bit 11 to 0 as the number of byte declared in bit [15:12] is the write data to the flash device.
    4. Set bit [15:12] to 1 as you be writing 1 byte (8 bits) of data into the status register.
  3. Write the data to set the sector protection into the flash command write data 0 register.
    1. Bit 6 and bit [4:2] of the status register are the block protect bits and bit 5 is the Top/Bottom bit. In this example, protection is required for all sectors from the bottom of the memory array. For more information, refer to the respective flash datasheet.
  4. Write 1 to bit 0 of the flash command control register to start the write status register for the sector protect operation.