1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Intel HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.2. Device Family Support
The Generic Serial Flash Interface IP is supported in the following devices:
2 Export the flash pin by enabling the Enable SPI pins interface parameter of this IP.
3 The IP can only access flash that is connected to FPGA GPIO pins. The IP cannot be used to access flash that is connected to SDM for configuration purpose.
4 The exported conduit pins, which have different Output Enable (OE) signals, should not be placed in the same x4 DQ group. Error(175005) may trigger due to the OE conflict during compilation. Refer to the Intel® Agilex™ General Purpose I/O and LVDS SERDES User Guide and the KDB Answer Error (175005): Could not find a location with: GPIO_SHARED_NOE0 of (locations affected) for more information.
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