Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 4/20/2022
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Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Nios II HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Intel® Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash 1.8.6. Program Flash
1.9. Nios II HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.6. Using Generic Serial Flash Interface Intel® FPGA IP

The Generic Serial Flash Interface Intel® FPGA IP core interfaces are Avalon® memory-mapped compliant. For more details, refer to the Avalon® specification.
Note:
  • For operations that require write value to flash, you must perform write enable operation first.
  • You must read the flag status register every time you issue a write or erase command.
  • In case of support multiples flash devices, you must write chip select register to select the correct flash device before performing any operation to the specific flash device.

Section Content
Control Status Register Byte Enable
Memory Operations
Byte Enabling
Constraining the I/O Pins

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