Generic Serial Flash Interface Intel® FPGA IP User Guide

ID 683419
Date 4/20/2022

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Document Table of Contents

1.2. Device Family Support

The Generic Serial Flash Interface IP is supported in the following devices:

  • Intel® Agilex™ 2 3 4
  • Intel® Stratix® 10 2 3
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Intel® Cyclone® 10 LP
  • Intel® MAX® 10 (For general purpose memory only) 2
  • Stratix® V
  • Arria® V
  • Cyclone® V
  • Stratix® IV
  • Cyclone® IV
  • Arria® II
2 Export the flash pin by enabling the Enable SPI pins interface parameter of this IP.
3 The IP can only access flash that is connected to FPGA GPIO pins. The IP cannot be used to access flash that is connected to SDM for configuration purpose.
4 The exported conduit pins, which have different Output Enable (OE) signals, should not be placed in the same x4 DQ group. Error(175005) may trigger due to the OE conflict during compilation. Refer to the Intel® Agilex™ General Purpose I/O and LVDS SERDES User Guide and the KDB Answer Error (175005): Could not find a location with: GPIO_SHARED_NOE0 of (locations affected) for more information.