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1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Nios II HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
184.108.40.206. Byte Enabling Supported Patterns
|Byte Enable Pattern||Support|
|4'b0000||Supported (when burst is more than 1)|
All write bursts greater than 1 is set to byte enable of 4’b1111, in which all byte enables are asserted through all the words of the burst. When a master wider than 32 bits is used to connect to the IP, the interconnect fabric of the Platform Designer produces multi-word bursts to adapt the wide master into the narrow 32-bit slave (the IP). Choose to use the byte enabling patterns in the Byte Enabling Supported Patterns table if the wide master intends to write only certain bytes in the entire transaction. You must ensure that the byte enabling pattern is contiguous for burst writes.
Note: For burst writes, the IP writes all bytes (4'b1111) into the flash even with your selected byte enable pattern. If you have not enabled the data, the IP writes 0xFF. The performance of the IP is still the same as writing 8 bytes for a 64-bit wide master, even if you have enabled only 1 byte using byte enable.
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