1.6.2. Memory Operations
During flash memory access, the IP performs the following steps to allow you to perform any direct read or write operation:
- Write enable for write operation
- Check flag status register to make sure the operation has been completed at the flash
- Release waitrequest signal when operation completed
Memory operations are Avalon® memory-mapped operations. You must set the correct address on the address bus, write data if it is write transaction, drive burst count bus 1 if single transaction or desired burst count value and trigger the write or read signal.
There are two internal unconstrained clocks in the Generic Flash Serial Interface Intel® FPGA IP core when you compile your design in the Intel® Quartus® Prime Pro Edition software. Intel® recommends that you constraint the path by using the following command:
create_generated_clock -name <name_of_generated_clock> -source [get_ports <input_clock_name>] -divide_by 2 [get_registers <path_of_the_unconstrained_path>]