Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 4/20/2022
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Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Nios II HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Intel® Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash 1.8.6. Program Flash
1.9. Nios II HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.5. Register Map

Table 4.  Register Map
  • Each address offset in the following table represents 1 word of memory address space.
  • IP_CLK is the clock that drives the IP.
  • SCLK is the clock that drives the flash device.
Offset (Hex) Register Name R/W Field Name Bit Default Value (Hex) Description
0 Control Register Reserved 31:9 Reserved
R/W Addressing mode 8 0x0

Addressing mode for read and write operation:

  • 0x0: 3-bytes addressing.
  • 0x1: 4-bytes addressing.

For 4-byte addressing mode, you must enable 4-byte address by sending command to the flash.

This bit affects direct access to memory via the Avalon® memory-mapped interface for both write and read operation.
R/W Chip select 7:4 0x0 Selects the flash device.
  • 0x0: To select first device.
  • 0x1: To select second device.
  • 0x2: To select third device.
Reserved 3:1 Reserved
R/W Enable 0 0x1 Set this bit to 0 to disable the output of the IP and put all output signal to high impedance state. This can be used to share bus with other devices.
1 SPI Clock Baud-rate Register Reserved 31:5 Reserved
R/W Baud rate divisor 4:0 0x10

The IP has an internal clock divider to generate the clock that connects to the flash device. The possible divisor value is from 2 to 32 with the increment of 2.

So, the maximum clock that the flash run is half of the clock of the IP. Ex if the IP is run with 100 Mhz clock, then the clock of the flash is at 50 Mhz.

By default, the clock is set to the lowest clock (/32) to ensure that the IP works in most cases.

Divisor values:

  • 0x1 : /2
  • 0x2 : /4
  • 0x3 : /6
  • ...
  • 0xF : /30
  • 0x10 : /32
2 CS Delay Setting Register Reserved 31:12 Reserved
R/W tSHSL (CS High Time) 11:8   This register setting controls the tSHSL.
  • 0: tSHSL is 3 IP_CLK.
  • n: tSHSL is 3+n IP_CLK.
R/W CS de-assert (CS Active Hold Time) 7:4 0x0 Sets the chip select de-assertion delay.
  • 0: Chip select is de-asserted at the last falling edge of SCLK.
  • n: Chip select is de-asserted n number of clocks after the last falling edge of SCLK.
R/W CS assert (CS Active Setup Time) 3:0 0x0 Sets the chip select assertion delay.
  • 0: Chip select is asserted half flash clock period before the first rising edge of SCLK.
  • n: Chip select is asserted half flash clock period plus n number of IP_CLK.6
3 Read Capturing Register Reserved 31:4 Reserved
R/W Read delay 3:0 0x0 The clock to output timing of the flash plus the board trace, I/O pin timing can contribute to high value of delay to the data arriving at the IP logic. The delay capture provides a way for the IP to delay its reading logic to compensate for those delays.

Delay the read data logic by a value of the IP_CLK cycles.

4 Operating Protocols Setting Register Reserved 31:18 Reserved
R/W Read data out transfer mode 17:16 0x0 Transfer mode for read data output.
Reserved 15:14 Reserved
R/W Read address transfer mode 13:12 0x0 Transfer mode for read address input Description as bit 1:0.
Reserved 11:10 Reserved
R/W Write Data in transfer mode 9:8 0x0 Transfer mode for write data input Description as bit 1:0.
Reserved 7:6 Reserved
R/W Write address transfer mode 5:4 0x0 Transfer mode for write address input Description as bit 1:0.
Reserved 3:2 Reserved
R/W Instruction transfer mode 1:0 0x0 Transfer mode for opcode:
  • 0x0: Standard SPI mode – command input is sent on DQ0.
  • 0x1: Dual I/O mode – command input is sent on DQ[1:0].
  • 0x2: Quad I/O mode – command input is sent on DQ[3:0].
This setting affects the flash command register. For example, if this field is set to 0x1, flash common operations (such as read id, read status, write status register) uses 0x1 as well.
5 Read Instruction Register Reserved 31:13 Reserved
R/W Dummy cycles 12:8 0x0 Number of default dummy cycles used for read operation. Refer to the respective flash device datasheet.
R/W Read opcode 7:0 0x03 The opcode for read operation. Refer to the respective flash device datasheet to select the correct opcode according to the transfer mode setting.
6 Write Instruction Register Reserved 31:16 Reserved
R/W Polling opcode 15:8 0x05

The opcode to check if the write operation has been completed. After write operation is completed, the IP releases the wait request of the Avalon® memory-mapped interface.

In applicable devices, you can set as the status register or flag status register.
R/W Write opcode 7:0 0x02 The opcode for write operation. Refer to the respective flash device datasheet to select the correct opcode according to the transfer mode setting.
7 Flash Command Setting Register7 Reserved 31:21 Reserved
R/W Number of dummy cycles 20:16 0x0 The number of dummy cycles. Set to 0 when the operation does not require any dummy cycles. Refer to the respective flash device datasheet for dummy clock requirements.
R/W Number of data bytes 15:12 0x08 The number of write or read data. This works together with bit 11. If the value is Set to 0 if the operation has no write or read data, for example, write enable.
R/W Data type 11 0x01

Indicates the type of data (bit [15:12]).

  • 0: Number of byte declared in [15:12] is write data to flash device
  • 1: Number of byte declared in [15:12] is read data from flash device
R/W Number of address bytes 10:8 0x0

Number of address bytes to send to the flash device. Either 3 or 4 bytes

If this is set to zero then the operation does not carry any address byte.
R/W Opcode 7:0 0x05 The opcode of the operation.
8 Flash Command Control Register Reserved 31:1 Reserved
W Start 0 0x0 Write 1 to this bit to start the operation.
9 Flash Command Address Register R/W Stating address 31:0 31:0 Address of flash command.
A Flash Command Write Data 0 Register R/W Lower 4 bytes write data 31:0 0x0 The first 4-byte of write data to flash device.
B Flash Command Write Data 1 Register R/W Upper 4 bytes write data 31:0 0x0 The last 4-byte of write data to the flash device.
C Flash Command Read Data 0 Register R Lower 4 bytes read data 31:0 0x0 The first 4-byte of read data from flash device.
D Flash Command Read Data 1 Register R Upper 4 bytes read data 31:0 0x0 The last 4-byte of read data from the flash device.
6 Intel® recommends that you set the chip select assertion delay to 5 if you are running the IP clock at 100 MHz.
7 Default setting is for read status command.
Level Two Title