A newer version of this document is available. Customers should click here to go to the newest version.
1.5. Register Map
|Offset (Hex)||Register Name||R/W||Field Name||Bit||Default Value (Hex)||Description|
Addressing mode for read and write operation:
For 4-byte addressing mode, you must enable 4-byte address by sending command to the flash.This bit affects direct access to memory via the Avalon® memory-mapped interface for both write and read operation.
|R/W||Chip select||7:4||0x0||Selects the flash device.
|R/W||Enable||0||0x1||Set this bit to 0 to disable the output of the IP and put all output signal to high impedance state. This can be used to share bus with other devices.|
|1||SPI Clock Baud-rate Register||Reserved||31:5||Reserved|
|R/W||Baud rate divisor||4:0||0x10||
The IP has an internal clock divider to generate the clock that connects to the flash device. The possible divisor value is from 2 to 32 with the increment of 2.
So, the maximum clock that the flash run is half of the clock of the IP. Ex if the IP is run with 100 Mhz clock, then the clock of the flash is at 50 Mhz.
By default, the clock is set to the lowest clock (/32) to ensure that the IP works in most cases.
|2||CS Delay Setting Register||Reserved||31:12||Reserved|
|R/W||tSHSL (CS High Time)||11:8||This register setting controls the tSHSL.
|R/W||CS de-assert (CS Active Hold Time)||7:4||0x0||Sets the chip select de-assertion delay.
|R/W||CS assert (CS Active Setup Time)||3:0||0x0||Sets the chip select assertion delay.
|3||Read Capturing Register||Reserved||31:4||Reserved|
|R/W||Read delay||3:0||0x0||The clock to output timing of the flash plus the board trace, I/O pin timing can contribute to high value of delay to the data arriving at the IP logic. The delay capture provides a way for the IP to delay its reading logic to compensate for those delays.
Delay the read data logic by a value of the IP_CLK cycles.
|4||Operating Protocols Setting Register||Reserved||31:18||Reserved|
|R/W||Read data out transfer mode||17:16||0x0||Transfer mode for read data output.|
|R/W||Read address transfer mode||13:12||0x0||Transfer mode for read address input Description as bit 1:0.|
|R/W||Write Data in transfer mode||9:8||0x0||Transfer mode for write data input Description as bit 1:0.|
|R/W||Write address transfer mode||5:4||0x0||Transfer mode for write address input Description as bit 1:0.|
|R/W||Instruction transfer mode||1:0||0x0||Transfer mode for opcode:
|5||Read Instruction Register||Reserved||31:13||Reserved|
|R/W||Dummy cycles||12:8||0x0||Number of default dummy cycles used for read operation. Refer to the respective flash device datasheet.|
|R/W||Read opcode||7:0||0x03||The opcode for read operation. Refer to the respective flash device datasheet to select the correct opcode according to the transfer mode setting.|
|6||Write Instruction Register||Reserved||31:16||Reserved|
The opcode to check if the write operation has been completed. After write operation is completed, the IP releases the wait request of the Avalon® memory-mapped interface.In applicable devices, you can set as the status register or flag status register.
|R/W||Write opcode||7:0||0x02||The opcode for write operation. Refer to the respective flash device datasheet to select the correct opcode according to the transfer mode setting.|
|7||Flash Command Setting Register7||Reserved||31:21||Reserved|
|R/W||Number of dummy cycles||20:16||0x0||The number of dummy cycles. Set to 0 when the operation does not require any dummy cycles. Refer to the respective flash device datasheet for dummy clock requirements.|
|R/W||Number of data bytes||15:12||0x08||The number of write or read data. This works together with bit 11. If the value is Set to 0 if the operation has no write or read data, for example, write enable.|
Indicates the type of data (bit [15:12]).
|R/W||Number of address bytes||10:8||0x0||
Number of address bytes to send to the flash device. Either 3 or 4 bytesIf this is set to zero then the operation does not carry any address byte.
|R/W||Opcode||7:0||0x05||The opcode of the operation.|
|8||Flash Command Control Register||Reserved||31:1||Reserved|
|W||Start||0||0x0||Write 1 to this bit to start the operation.|
|9||Flash Command Address Register||R/W||Stating address||31:0||31:0||Address of flash command.|
|A||Flash Command Write Data 0 Register||R/W||Lower 4 bytes write data||31:0||0x0||The first 4-byte of write data to flash device.|
|B||Flash Command Write Data 1 Register||R/W||Upper 4 bytes write data||31:0||0x0||The last 4-byte of write data to the flash device.|
|C||Flash Command Read Data 0 Register||R||Lower 4 bytes read data||31:0||0x0||The first 4-byte of read data from flash device.|
|D||Flash Command Read Data 1 Register||R||Upper 4 bytes read data||31:0||0x0||The last 4-byte of read data from the flash device.|
Did you find the information on this page useful?