AN 805: Hierarchical Partial Reconfiguration of a Design on Intel® Arria® 10 SoC Development Board

ID 683409
Date 11/06/2017

Document Revision History

Table 5.  Document Revision History
Document Version Software Version Changes



  • Updated the Reference Design Requirements section with software version
  • Updated the Flat Reference Design without PR Partitioning figure with design block changes
  • Updated the Reference Design Files table with information on the module
  • Updated the Partial Reconfiguration IP Core Integration figure with design block changes
  • Updated the figures - Design Partitions Window and Logic Lock Regions Window to reflect the new GUI
  • File name changes
  • Text edits



Initial release of the document