AN 805: Hierarchical Partial Reconfiguration of a Design on Intel® Arria® 10 SoC Development Board

ID 683409
Date 11/06/2017

Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board

Updated for:
Intel® Quartus® Prime Design Suite 17.1
This application note demonstrates transforming a simple design into a hierarchically partially reconfigurable design, and implementing the design on the Intel® Arria® 10 SoC development board.

Hierarchical partial reconfiguration (HPR) is a special type of partial reconfiguration (PR), where you contain a PR region within another PR region. You can create multiple personas for both the child and parent partitions. You nest the child partitions within their parent partitions. Reconfiguring a child partition does not impact operation in the parent or static regions. Reconfiguring a parent partition does not impact the operation in the static region, but replaces the child partitions of the parent region with default child partition personas. This methodology is effective in systems where multiple functions time-share the same FPGA device resources.

Partial reconfiguration provides the following advancements to a flat design:
  • Allows run-time design reconfiguration
  • Increases scalability of the design
  • Reduces system down-time
  • Supports dynamic time-multiplexing functions in the design
  • Lowers cost and power consumption through efficient use of board space
  • Implementation of this reference design requires basic familiarity with the Intel® Quartus® Prime FPGA implementation flow and knowledge of the primary Intel® Quartus® Prime project files.