AN 805: Hierarchical Partial Reconfiguration of a Design on Intel® Arria® 10 SoC Development Board

ID 683409
Date 11/06/2017

Step 4: Allocating Placement and Routing Region for PR Partitions

When you create the base revision, the PR design flow uses your PR partition region allocation to place the corresponding persona core in the reserved region. To locate and assign the PR region in the device floorplan for your base revision:
  1. Right-click the u_blinking_led_child instance in the Project Navigator and click Logic Lock Region > Create New Logic Lock Region. The region appears on the Logic Lock Regions Window.
  2. Your placement region must enclose the blinking_led_child logic. Select the placement region by locating the node in Chip Planner. Right-click the u_blinking_led_child region name in the Project Navigator and click Locate Node > Locate in Chip Planner.
    Figure 5. Chip Planner Node Location for blinking_led
  3. In the Logic Lock Regions window, specify the placement region co-ordinates in the Origin column. The origin corresponds to the lower-left corner of the region. For example, to set a placement region with (X1 Y1) co-ordinates as (69 10), specify the Origin as X69_Y10. The Intel® Quartus® Prime software automatically calculates the (X2 Y2) co-ordinates (top-right) for the placement region, based on the height and width you specify.
    Note: This tutorial uses the (X1 Y1) co-ordinates - (69 10), and a height and width of 20 for the placement region. Define any value for the placement region, provided that the region covers the blinking_led_child logic.
  4. Enable the Reserved and Core-Only options.
  5. Double-click the Routing Region option. The Logic Lock Routing Region Settings dialog box appears.
  6. Select Fixed with expansion for the Routing type. Selecting this option automatically assigns an expansion length of 1.
    Note: The routing region must be larger than the placement region, to provide extra flexibility for the Fitter when the engine routes different personas.
  7. Repeat steps 1 -6 for the u_blinking_led instance. The parent-level placement region must fully enclose the corresponding child-level placement and routing regions, while allowing sufficient space for the parent-level logic placement. This tutorial uses the (X1 Y1) co-ordinates - (66 7), a height of 47, and width of 26 for the placement region of the u_blinking_led instance.
    Figure 6.  Logic Lock Regions Window
Verify that the blinking_led.qsf contains the following assignments, corresponding to your floorplanning:
set_instance_assignment -name PLACE_REGION "69 10 88 29" -to \
set_instance_assignment -name RESERVE_PLACE_REGION ON -to \
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to \
set_instance_assignment -name ROUTE_REGION "68 9 89 30" -to \

set_instance_assignment -name PLACE_REGION "66 7 112 32" -to u_blinking_led 
set_instance_assignment -name RESERVE_PLACE_REGION ON -to u_blinking_led 
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to u_blinking_led 
set_instance_assignment -name ROUTE_REGION "65 6 113 33" -to u_blinking_led