F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683372
Date 12/17/2021
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Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Programmed Input/Output Design Example Functional Description 2.3. Programmed Input/Output Design Example Simulation Testbench 2.4. Single Root I/O Virtualization (SR-IOV) Design Example 2.5. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.6. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2. Programmed Input/Output Design Example Functional Description x
2.2.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.2. PIO Application (APPS) 2.2.3. On-Chip Memory (MEM) 2.2.4. F-Tile Reference and System PLL Clocks IP 2.2.5. Reset Release IP
2.2.2. PIO Application (APPS) x
2.2.2.1. Scheduler 2.2.2.2. Read Write Module 2.2.2.3. Avalon-MM Interface 2.2.2.4. Completion Module 2.2.2.5. Width Adapter
2.5. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.5.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.5.2. SR-IOV Applications (APPS)
2.5.2. SR-IOV Applications (APPS) x
2.5.2.1. Access Parser 2.5.2.2. Access Router 2.5.2.3. Completion 2.5.2.4. PF Segram 2.5.2.5. VF Segram 2.5.2.6. F-Tile Reference and System PLL Clocks IP 2.5.2.7. Reset Release IP
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Installing the Linux Kernel Driver 3.6. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Testbench
3.3.1. Testbench x
3.3.1.1. Test Driver Module 3.3.1.2. PIO Design Example Testbench 3.3.1.3. SR-IOV Design Example Testbench
3.6. Running the Design Example x
3.6.1. Running the PIO Design Example 3.6.2. Running the SR-IOV Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.12.17 21.4
  • SR-IOV Design Example related information added to Design Example Description chapter
  • SR-IOV Design Example related information added to Quick Start Guide chapter
  • Generating tile files information added to Quick Start Guide chapter
  • Xcelium simulator information added to Steps to run simulation table
  • Running the SR-IOV Design Example section added to Quick Start Guide chapter
2021.10.04 21.3
  • Updated Configurations Supported by the F-Tile Avalon-ST Design Examples Table
  • Added PCIe Gen3/Gen4 x8 Design Example Variant block diagram
  • Added PIO Application (APPS) component information in Functional Description
  • Added Block Diagram for the PCIe x8 PIO Design Example Simulation Testbench block diagram
  • Added Platform Designer System Contents for F-Tile Avalon®-ST IP for PCI Express PIO Design Example Gen4 x8 variant screenshot
  • Update figure Directory Structure for the Generated Design Example
  • Procedure updated in Simulating the Design Example
  • Added VCSMX simulator information to Steps to Run Simulation table.
2021.07.31 21.2 Initial Release
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