F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 12/17/2021
Public

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Document Table of Contents

5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.12.17 21.4
  • SR-IOV Design Example related information added to Design Example Description chapter
  • SR-IOV Design Example related information added to Quick Start Guide chapter
  • Generating tile files information added to Quick Start Guide chapter
  • Xcelium simulator information added to Steps to run simulation table
  • Running the SR-IOV Design Example section added to Quick Start Guide chapter
2021.10.04 21.3
  • Updated Configurations Supported by the F-Tile Avalon-ST Design Examples Table
  • Added PCIe Gen3/Gen4 x8 Design Example Variant block diagram
  • Added PIO Application (APPS) component information in Functional Description
  • Added Block Diagram for the PCIe x8 PIO Design Example Simulation Testbench block diagram
  • Added Platform Designer System Contents for F-Tile Avalon®-ST IP for PCI Express PIO Design Example Gen4 x8 variant screenshot
  • Update figure Directory Structure for the Generated Design Example
  • Procedure updated in Simulating the Design Example
  • Added VCSMX simulator information to Steps to Run Simulation table.
2021.07.31 21.2 Initial Release