F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 12/17/2021
Public

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2.2.4. F-Tile Reference and System PLL Clocks IP

This IP is required for F-Tile PCIe interface implementation to configure the reference clock for the FGT PMA and System PLL. The clock from this IP is an logical connection. It is physically inside the F-Tile Avalon-ST IP for PCI Express Hard IP. There is no clock gating requirement at the design example level. The main clock of the PIO design example originates from coreclkout_hip of F-Tile Avalon-ST IP for PCI Express Hard IP running at 500 MHz. The clock originates from System PLL. This IP is required for F-Tile PCIe interface implementation to configure the reference clock for the FGT PMA and System PLL.