F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 12/17/2021
Public
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Document Table of Contents

1. Acronyms

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 4.0.0
Table 1.  Terms and Definitions
Term Definition

AVMM

Avalon Memory Mapped

AVST

Avalon Streaming

BAM

Burst Avalon Master

CplD

Completion with Data

DUT

Design Under Test

DW

Double Word

ED

Example Design

FBE

First Byte Enable

FIFO

First In First Out

PIO

Programmed Input/Output

LBE

Last Byte Enable

MPS

Maximum Payload Size

MRd

Memory Read

MWr

Memory Write

RX

Receiver

QHIP

Quartus IP

TLP

Transaction Layer packet

TX

Transmit

SR-IOV

Single Root Input/Output Virtualization

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