Low Latency 100G Ethernet Design Example User Guide

ID 683371
Date 11/08/2017

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 16.1

The Arria® 10 variations of the LL 100GbE IP core feature a simulatable testbench and a hardware design example that supports compilation and hardware testing, to help you understand usage. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled hardware design to the Arria® 10 GX Transceiver Signal Integrity Development Kit. The testbench and demonstration design example are available for a wide range of parameters. However, they do not cover all possible parameterizations of the LL 100GbE IP Core.

In addition, for most IP core variations, Intel® provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

Figure 1. Development Steps for the Design Example