Low Latency 100G Ethernet Design Example User Guide

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ID 683371
Date 11/08/2017
Public

A. Document Revision History

Table 7.  Revision History
Date Changes
2017.11.08 Added link to KDB Answer that provides workaround for potential jitter on Arria® 10 devices due to cascading ATX PLLs in the IP core. Refer to Generating the Design and Compiling and Testing the Design Example in Hardware.
Note: This design example user guide has not been updated to reflect minor changes in design generation in Quartus® Prime releases later than the Quartus® Prime software relase v16.1.
2016.11.23
  • Updated for Quartus® Prime software v16.1. Refer to Directory Structure and various Related References links updated for the separation of the Low Latency 100-Gbps Ethernet IP Core User Guide from the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core User Guide.
  • Updated to refer to design example rather than example design.
  • Corrected assorted typos and minor errors.
2016.05.02 Initial release
Level Two Title