Low Latency 100G Ethernet Design Example User Guide

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ID 683371
Date 11/08/2017
Public

2.5. Interface Signals

Table 4.   LL 100GbE Design Example Interface Signals
Signal Direction Interface
clk_ref Input Clocks
reset_async Input Reset
tx_serial[3:0] (CAUI-4 variations) or tx_serial[9:0] (standard variations) Output Transceiver PHY serial data interface
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