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2.1.2. Enabling Your Design For the Link Monitor
To enable the use of Link Monitor, your design must instantiate JTAG to Avalon® Master Bridge. The availability of the JTAG to Avalon® Master bridge in the Intel® Stratix® 10 Ethernet IP cores is shown in the following table.
Device | IP Core | Data Rate (Gbps) | IP Type | Design Example 2 | Standalone IP 3 |
---|---|---|---|---|---|
Intel® Stratix® 10 L-Tile | 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP | 10 | Soft | Yes | Yes |
25G Ethernet Intel® FPGA IP | 25 | Soft | Yes | N/A | |
Low Latency 40G Ethernet Intel® FPGA IP | 40 | Soft | Yes | Yes | |
Low Latency 100G Ethernet Intel® FPGA IP | 100 | Soft | Yes | Yes | |
Intel® Stratix® 10 H-Tile | 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP | 10 | Soft | Yes | Yes |
25G Ethernet Intel® FPGA IP | 25 | Soft | Yes | N/A | |
Low Latency 40G Ethernet Intel® FPGA IP | 40 | Soft | Yes | Yes | |
Low Latency 100G Ethernet Intel® FPGA IP | 100 | Soft | Yes | Yes | |
H-Tile Hard IP for Ethernet Intel® FPGA IP | 50 | Hard | Yes | Yes | |
100 | Hard | Yes | Yes | ||
Intel® Stratix® 10 E-Tile | E-Tile Hard IP for Ethernet Intel® FPGA IP | 10 | Hard | Yes | Yes |
25 | Hard | Yes | Yes | ||
100 (25Gx4-NRZ) |
Hard | Yes | Yes | ||
100 (50Gx2-PAM4) |
Hard | Yes | Yes |
Related Information
2 Design examples generated in Intel® Quartus® Prime Pro Edition software are instantiated with JTAG to Avalon® Master Bridge. These design examples also include Ethernet Packet Generators that can be controlled using the Link Monitor.
3 Supported standalone IPs provide an option called Enable JTAG to Avalon® Master Bridge in the respective IP Parameter Editor GUI in Intel® Quartus® Prime Pro Edition software. The selection of this option automatically includes JTAG to Avalon® Master Bridge during IP generation. This JTAG to Avalon® Master Bridge do not provide access to Packet Generators, which is originally part of design example. For non-supported standalone IPs, the JTAG to Avalon® Master Bridge has to be manually instantiated from the IP Catalog. Refer to respective IP design example RTL and user guides for more details on IP connections.
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