Intel® Acceleration Stack User Guide: Intel® FPGA Programmable Acceleration Card N3000-N/2
ID
683362
Date
11/01/2021
Public
1. About this Document
2. System Requirements
3. Hardware Installation
4. Installing the OPAE Software
5. Identify the Intel® MAX® 10 BMC Version
6. Intel XL710 Driver Installation and Firmware Update
7. Updating the Retimer Firmware
8. OPAE Tools
9. Sample Test: Native Loopback
10. Configuring Ethernet Interfaces
11. Testing Network Loopback Using Data Plane Development Kit (DPDK)
12. Graceful Shutdown
13. Single Event Upset (SEU)
14. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000-N/2
A. Troubleshooting
B. fpgabist Sample Output
1. About this Document
| Updated for: |
|---|
| Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.3.1 |
This document provides:
- Instructions and requirements for installing the Intel® FPGA Programmable Acceleration Card N3000-N/2 (BD-NVV-N3000-3 or BD-NVV-N3000-2) into a server.
- Instructions for installing the Open Programmable Acceleration Engine (OPAE) software on host Intel® Xeon® processor for managing and accessing the Intel® FPGA PAC N3000-N/2.
- Instructions for installing the OPAE tools for validation of the Intel® FPGA PAC N3000-N/2.
- Instructions for running built-in self-tests using the FPGA factory image.
- Instructions for installing the Intel XL710 driver and network testing tools for testing the Ethernet capabilities.
- Information about Graceful Shutdown and Single Event Upset (SEU) handling.
The Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs is a collection of software, firmware, and tools that allows both software and RTL developers to take advantage of the power of Intel® FPGA PAC N3000-N/2. By offloading computationally intensive networking tasks to the FPGA, the acceleration platform allows the Intel® Xeon® processor to execute other critical processing tasks.
Figure 1. Block Diagram