Intel® Acceleration Stack User Guide: Intel® FPGA Programmable Acceleration Card N3000-N/2

ID 683362
Date 11/01/2021
Document Table of Contents

10.5. Ethernet Link Status

The external Ethernet link is connected directly to the retimer device. The link status of the external Ethernet link is obtained from the retimer. The Intel® Arria® 10 FPGA and Intel XL710 device have status indications for Ethernet link status, however these are status of internal links between components.

You must obtained the Ethernet link status from the Retimers. You can obtain the Ethernet link status either using the OPAE fpgainfo phy command or using the following sysfs node which can be read for link status:
$ cat /sys/bus/spi/drivers/intel-max10/spi0.0/pkvl/status
If your server has more than one Intel® FPGA PAC N3000-N/2 installed, then the following sysfs node must correspond to the desired Intel® FPGA PAC N3000-N/2.
Use the PCIe B:D.F of the desired Intel® FPGA PAC N3000-N/2 to determine the proper value of <X>. The value returned from this sysfs node is a bit level representation of link status where 1 corresponds to link up and 0 is link down.
  • Bits [0:3] corresponds to links 0-3 of QSFP A
  • Bits [4:7] corresponds to links 0-3 of QSFP B
For example, consider a returned value of 0x33:
QSFP Link 3 Link 2 Link 1 Link 0
QSFP A 0 = Link Down 0 = Link Down 1 = Link Up 1 = Link Up
QSFP B 0 = Link Down 0 = Link Down 1 = Link Up 1 = Link Up

For 4x25G network configuration, only QSFP A is used and links 0-3 are valid. For 2x2x25G network configuration, both QSFP A and B are used, however only links 1 and 0 are valid.