Intel® Acceleration Stack User Guide: Intel® FPGA Programmable Acceleration Card N3000-N/2

ID 683362
Date 11/01/2021
Document Table of Contents

5.1. FPGA Factory Image Overview

The Intel® FPGA PAC N3000-N/2 has an on-board flash with two partitions (user and factory) for storing two FPGA image files known as user image and factory image. A new Intel® FPGA PAC N3000-N/2 is provided with the 2x2x25G image in factory partition and 4x25G image in user partition.

When the image in the user partition fails to load, the Intel® FPGA PAC N3000-N/2 reverts back and boots from factory partition. This factory image loaded into the user partition provides basic functionality to demonstrate all the interfaces including Ethernet and external memory interfaces.

The typical use case is a specific workload (for example: FLEXRan, ipSEC, vBNG, etc.) is loaded into the user partition. When the Intel® FPGA PAC N3000-N/2 is power cycled with a RSU command or a server power cycle, the user partition image is loaded into the Intel® Arria® 10 FPGA. The ability to load application specific images is a key benefit of the Intel® FPGA PAC N3000-N/2.

The factory image includes the following Intellectual Property (IP) to support in the development of Accelerator Function (AF):
  • The PCIe IP core
  • The Core Cache Interface protocol (CCI-P) fabric
  • DDR4 memory interface controller IP
  • QDR4 memory interface controller IP
  • 25 and 40 GbE physical interface and MACs with pass-through connectivity between Intel® Ethernet Connection C827 Retimer and Intel® Ethernet Controller XL710-BM2
  • FPGA Management Engine (FME)
  • Nios® core to configure the Intel Ethernet Connection C827 Retimers
Figure 8. Example: Factory Image for 2x2x25G