Intel® Stratix® 10 Avalon® Streaming (Avalon-ST) IP for PCIe* Design Example User Guide

ID 683361
Date 3/07/2022

2.3. Registers

There are no control registers for the PIO design example. The PCI Express Base Specification 3.0 defines a comprehensive set of configuration, control, and status registers to control and debug the design example.

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