1.5. Simulating the Design Example
- Change to the testbench simulation directory, pcie_example_design_tb.
- Run the simulation script for the simulator of your choice. Refer to the table below.
- Analyze the results.
|Xcelium* Parallel Simulator||<example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/xcelium||
This testbench simulates up to x8 variants. It supports x16 variants by down-training to x8. To simulate all lanes of a x16 variant, you can create a simulation model using the Platform Designer to use in an Avery testbench. For more information refer to AN-811: Using the Avery BFM for PCI Express* Gen3x16 Simulation on Intel Stratix 10 Devices.
The simulation reports, "Simulation stopped due to successful completion" if no errors occur.
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