1.4. Generating the Design Example
- In the Intel® Quartus® Prime Pro Edition software, create a new project ( ).
- Specify the Directory, Name, and Top-Level Entity.
- For Project Type, accept the default value, Empty project. Click Next.
- For Add Files click Next.
- For Family, Device & Board Settings under Family, select Intel® Stratix® 10 (GX/SX/MX/TX) and the Target Device for your design.
- Click Finish.
- In the IP Catalog, locate and add the Intel L-/H-Tile Avalon-ST for PCI Express IP.
- In the New IP Variant dialog box, specify a name for your IP. Click Create.
- On the IP Settings tabs, specify the parameters for your IP variation.
- On the Example Designs tab, make the following selections:
- For Available Example Designs, select PIO. This example design is for Endpoints only. No Root Port example design is available for the Intel® Stratix® 10 Avalon® Streaming (Avalon-ST) IP for PCIe in the current Intel® Quartus® Prime release.
- For Example Design Files, turn on the Simulation and Synthesis options. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the example design generation time.
- If you have selected a x16 configuration, for Select simulation Root Complex BFM, choose the appropriate BFM:
- Intel FPGA BFM: for all configurations up to Gen3 x8. This bus functional model (BFM) supports x16 configurations by downtraining to x8.
- Third-party BFM: for x16 configurations if you want to simulate all 16 lanes using a third-party BFM. Refer to AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel Stratix 10 Devices for information about simulating with the Avery BFM.
- For Generated HDL Format, only Verilog is available in the current release.
- For Target Development Kit, select the appropriate option.
Note: If you select None, the generated design example targets the device you specified in Step 5 above. You cannot change the pin allocations of the Intel L-/H-Tile Avalon-MM for PCI Express IP in the Intel® Quartus® Prime project. However, this IP does support lane reversal and polarity inversion on the PCB by default.
- Click Finish. You may save your .ip file when prompted, but it is not required to be able to use the example design.
- The prompt, Recent changes have not been generated. Generate now?, allows you to create files for simulation and synthesis of the IP core variation that you specified in Step 9 above. Click No if you only want to work with the design example you have generated.
- Close the dummy project.
- Open the example design project.
- Compile the example design project to generate the .sof file for the complete example design. This file is what you download to a board to perform hardware verification.
- Close your example design project.
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