A.2. Matrix Multiplication Library
When you use the matrix multiplication library, you can affect the number of DSP blocks and RAM blocks by controlling the dot product vector size and the number of matrix elements read at one time. Increasing the dot product vector size can achieve better latency, but at the cost of using more DSP blocks and other FPGA resources.
The header file is self-documented. You can review the header file to learn how to use the matrix multiplication library in your component.
- The data type of the matrix elements (For example, int, float, long, double).
- The number of rows in matrix A.
- The number of columns in matrix A. This value also the number of rows in matrix B.
- The number of columns in matrix B.
The number of DSP blocks to use in a single computation. This value must be a factor of t_colsA.
You can achieve better component latency by increasing this value. However, you use more FPGA area to achieve this. Keeping this value low lowers your FPGA resource usage, but increases the latency.
- The number of elements to read at one time from matrix A. The default value of BLOCK_SIZE is the value of DOT_VEC_SIZE. You can reduce this number if the bandwidth needed by matrix A is lower than the value of DOT_VEC_SIZE, but it must remain a factor of DOT_VEC_SIZE.
- This parameter can be adjusted to try and improve the fMAX of a component that uses this library. Review the header file for a detailed description of this argument and its effects.