11.4. Creating Objects From RTL Code
You can create a library from object files that package register transfer level (RTL) language source files. An RTL-based object file also contains an object manifest file (in XML format) that identifies the functions that are callable in the object file. A library can contain multiple RTL-based objects.
Creating a library from RTL code is a two-step process. First, each object file is created from the RTL source and emulation models as described in the object manifest file with the fpga_crossgen command. Then, one or more object files are collected into an HLS library file with the fpga_libtool command.
To create a library from RTL code, you need to create the following files and components:
|File or Component||Description|
|RTL module source files||
Verilog (.v), System Verilog (.sv), or VHDL (.vhd) files and accompanying memory initialization files (.mif or .hex) that define the RTL modules in the library.
You cannot use additional files such as Intel® Quartus® Prime IP File (.qip), Synopsys Design Constraints File (.sdc), or Tcl Script File (.tcl).
|Object manifest file||An XML (.xml) file that describes the properties of the callable functions available in the RTL module.
The Intel® HLS Compiler uses these properties to integrate the RTL module in an HLS library into the component pipeline.
|RTL module function signature file||A C-style header file (.h) that declares the signatures of the functions that are implemented by the RTL module and described in the RTL module properties file.
Use this header file in your HLS component source code so that your component can call the functions provided in the HLS library.
|HLS emulation model files||C++ files (.cpp and .h) that contain code that is functionally equivalent to the RTL component and has the same function signatures as the RTL component. The emulation model is used only for component emulation. Simulations use the RTL provided in the library.|
Did you find the information on this page useful?