4.4. Avalon® Memory-Mapped Host Interfaces
Each mm_host argument of a component results in an input conduit for the address. That input conduit is associated with the component start and busy signals. In addition to this input conduit, a unique Avalon® MM Host interface is created for each address space. Host interfaces that share the same address space are arbitrated on the same interface.
// 32-bit wide word ihc::mm_master<uint32_t, ihc::dwidth<32>, ihc::awidth<16>, ihc::latency<0>, ihc::waitrequest<true>, ihc::aspace<1>> mm_a; uint32_t value = mm_a[0x0006];In contrast, the following code example results in 0x0006 on the mm_host interface because 0x0006 = 0x0006 << 2.
// 8-bit wide word ihc::mm_master<uint8_t, ihc::dwidth<32>, ihc::awidth<16>, ihc::latency<0>, ihc::waitrequest<true>, ihc::aspace<2>> mm_b; uint32_t value = mm_a[0x0006];
For more information about Avalon® MM Host interfaces, refer to "Avalon Memory-Mapped Interfaces" in Avalon Interface Specifications.
|Template Object or Parameter||Description|
|ihc::mm_host||The underlying pointer type.|
|ihc::dwidth||The width of the memory-mapped data bus in bits|
|ihc::awidth||The width of the memory-mapped address bus in bits.|
|ihc::aspace||The address space of the interface that associates with the host.|
|ihc::latency||The guaranteed latency from when a read command exits the component when the external memory returns valid read data.|
|ihc::maxburst||The maximum number of data transfers that can associate with a read or write transaction.|
|ihc::align||The alignment of the base pointer address in bytes.|
|ihc::readwrite_mode||The port direction of the interface.|
Adds the waitrequest signal that is asserted by the agent when it is unable to respond to a read or write request.
|getInterfaceAtIndex||This testbench function is used to index into an mm_host object.|