AN 770: Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board

ID 683345
Date 11/06/2017

Step 6: Creating Revisions

The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA. From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.

To compile a PR design, you must create a PR implementation revision and synthesis revision for each persona. In this reference design, the three personas contain a base revision, three separate synthesis revisions, and three separate implementation revisions:
Table 3.  Revisions for the Three Personas
Synthesis Revision Implementation Revision
blinking_led_default blinking_led_pr_alpha
blinking_led_slow blinking_led_pr_bravo
blinking_led_empty blinking_led_pr_charlie

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