AN 770: Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board

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ID 683345
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board
Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core Step 5: Defining Personas Step 6: Creating Revisions Step 7: Generating the Partial Reconfiguration Flow Script Step 8: Running the Partial Reconfiguration Flow Script Step 9: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 4: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core x
Updating the Top-Level Design
Step 6: Creating Revisions x
Creating Implementation Revisions Creating Synthesis-Only Revisions Specifying Revision Type
Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board

Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board

Updated for:
Intel® Quartus® Prime Design Suite 17.1
This application note demonstrates transforming a simple design into a partially reconfigurable design, and implementing the design on the Intel® Arria® 10 SoC development board.

Partial reconfiguration (PR) feature allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. Create multiple personas for a particular region in your design, without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA device resources.

Partial reconfiguration provides the following advancements to a flat design:
  • Allows run-time design reconfiguration
  • Increases scalability of the design
  • Reduces system down-time
  • Supports dynamic time-multiplexing functions in the design
  • Lowers cost and power consumption through efficient use of board space
Note:
  • Implementation of this reference design requires basic familiarity with the Intel® Quartus® Prime FPGA implementation flow and knowledge of the primary Intel® Quartus® Prime project files.
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