Intel® FPGA SDK for OpenCL™ Standard Edition: Programming Guide

ID 683342
Date 4/22/2019
Document Table of Contents XML Elements for ATTRIBUTES

In the XML specification file of the RTL module within an Intel® FPGA SDK for OpenCL™ library, there are XML elements under ATTRIBUTES that you can specify to set the module's characteristics.
Table 7.  XML Elements Associated with the ATTRIBUTES Element in the XML Specification File of an RTL Module
Attention: Except for IS_STALL_FREE and EXPECTED_LATENCY, all elements have safe values. If you are unsure which value you should specify for an attribute, set it to the safe value. Compiling your kernel with a library that uses safe values will result in functional hardware. However, the hardware might be larger than the actual size.
XML Element Description

Instructs the Intel® FPGA SDK for OpenCL™ Offline Compiler to remove all stall logic around the RTL module.

Set IS_STALL_FREE to "yes" to indicate that the module neither generates stalls internally nor can it properly handle incoming stalls. The module simply ignores its stall input. If you set IS_STALL_FREE to "no", the module must properly handle all stall and valid signals.

Note: If you set IS_STALL_FREE to "yes", you must also set IS_FIXED_LATENCY to "yes". Also, if the RTL module has an internal state, it must properly handle ivalid=0 inputs.

An incorrect IS_STALL_FREE setting will lead to incorrect results in hardware.


Indicates whether the RTL module has a fixed latency.

Set IS_FIXED_LATENCY to "yes" if the RTL module always takes known a number of clock cycles to compute its output. The value you assign to the EXPECTED_LATENCY element specifies the number of clock cycles.

The safe value for IS_FIXED_LATENCY is "no".

Note: For a given module, you may set IS_FIXED_LATENCY to "yes" and IS_STALL_FREE to "no". Such a module produces its output in a fixed number of clock cycles and handles stall signals properly.

Specifies the expected latency of the RTL module.

If you set IS_FIXED_LATENCY to "yes", the EXPECTED_LATENCY value indicates the number of pipeline stages inside the module. In this case, you must set this value to be the exact latency of the module. Otherwise, the offline compiler will generate incorrect hardware.

For a module with variable latency, the offline compiler balances the pipeline around this module to the EXPECTED_LATENCY value that you specify. The specified value and the actual latency might differ, which might affect the number of stalls inside the pipeline. However, the resulting hardware will be correct.


Specifies the number of multiple inputs that this module can process simultaneously. You must specify a value for CAPACITY if you also set IS_STALL_FREE="no" and IS_FIXED_LATENCY="no". Otherwise, you do not need to specify a value for CAPACITY.

If CAPACITY is strictly less than EXPECTED_LATENCY, the offline compiler will automatically insert capacity-balancing FIFO buffers after this module when necessary.

The safe value for CAPACITY is 1.

HAS_SIDE_EFFECTS Indicates whether the RTL module has side effects. Modules that have internal states or communicate with external memories are examples of modules with side effects.

Set HAS_SIDE_EFFECTS to "yes" to indicate that the module has side effects. Specifying HAS_SIDE_EFFECTS to "yes" ensures that optimization efforts do not remove calls to modules with side effects.

Stall-free modules with side effects (that is, IS_STALL_FREE="yes" and HAS_SIDE_EFFECTS="yes") must properly handle ivalid=0 input cases because the module might receive invalid data occasionally.

The safe value for HAS_SIDE_EFFECTS is "yes".

ALLOW_MERGING Instructs the offline compiler to merge multiple instances of the RTL module.

Set ALLOW_MERGING to "yes" to allow merging of multiple instances of the module. Intel® recommends setting ALLOW_MERGING to "yes".

The safe value for ALLOW_MERGING is "no".

Note: Marking the module with HAS_SIDE_EFFECTS="yes" does not prevent merging.