Intel® FPGA SDK for OpenCL™ Standard Edition: Programming Guide

Download PDF
ID 683342
Date 4/22/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Standard Edition Overview 2. Intel® FPGA SDK for OpenCL™ Offline Compiler Kernel Compilation Flows 3. Obtaining General Information on Software, Compiler, and Custom Platform 4. Managing an FPGA Board 5. Structuring Your OpenCL Kernel 6. Designing Your Host Application 7. Compiling Your OpenCL Kernel 8. Emulating and Debugging Your OpenCL Kernel 9. Reviewing Your Kernel's report.html File 10. Profiling Your OpenCL Kernel 11. Developing OpenCL™ Applications Using Intel® Code Builder for OpenCL™ 12. Intel® FPGA SDK for OpenCL™ Standard Edition Advanced Features A. Support Statuses of OpenCL Features B. Document Revision History of the Intel® FPGA SDK for OpenCL™ Standard Edition Programming Guide
1. Intel® FPGA SDK for OpenCL™ Standard Edition Overview x
1.1. Intel® FPGA SDK for OpenCL™ Standard Edition Programming Guide Prerequisites 1.2. Intel® FPGA SDK for OpenCL™ Standard Edition FPGA Programming Flow
2. Intel® FPGA SDK for OpenCL™ Offline Compiler Kernel Compilation Flows x
2.1. One-Step Compilation for Simple Kernels 2.2. Multistep Intel® FPGA SDK for OpenCL™ Standard Edition Design Flow
3. Obtaining General Information on Software, Compiler, and Custom Platform x
3.1. Displaying the Software Version (version) 3.2. Displaying the Compiler Version (-version) 3.3. Listing the Intel® FPGA SDK for OpenCL™ Standard Edition Utility Command Options (help) 3.4. Listing the Intel® FPGA SDK for OpenCL™ Offline Compiler Command Options (no argument, -help, or -h) 3.5. Listing the Available FPGA Boards in Your Custom Platform (-list-boards) 3.6. Displaying the Compilation Environment of an OpenCL Binary (env)
3.3. Listing the Intel® FPGA SDK for OpenCL™ Standard Edition Utility Command Options (help) x
3.3.1. Displaying Information on an Intel® FPGA SDK for OpenCL™ Utility Command Option (help <command_option>)
4. Managing an FPGA Board x
4.1. Installing an FPGA Board (install) 4.2. Uninstalling the FPGA Board (uninstall) 4.3. Querying the Device Name of Your FPGA Board (diagnose) 4.4. Running a Board Diagnostic Test (diagnose <device_name>) 4.5. Programming the FPGA Offline or without a Host (program <device_name>) 4.6. Programming the Flash Memory (flash <device_name>)
5. Structuring Your OpenCL Kernel x
5.1. Guidelines for Naming the Kernel 5.2. Programming Strategies for Optimizing Data Processing Efficiency 5.3. Programming Strategies for Optimizing Pointer-to-Local Memory Size 5.4. Implementing the Intel® FPGA SDK for OpenCL™ Standard Edition Channels Extension 5.5. Implementing OpenCL Pipes 5.6. Implementing Arbitrary Precision Integers 5.7. Using Predefined Preprocessor Macros in Conditional Compilation 5.8. Declaring __constant Address Space Qualifiers 5.9. Including Structure Data Types as Arguments in OpenCL Kernels 5.10. Inferring a Register 5.11. Enabling Double Precision Floating-Point Operations 5.12. Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
5.2. Programming Strategies for Optimizing Data Processing Efficiency x
5.2.1. Unrolling a Loop 5.2.2. Coalescing Nested Loops 5.2.3. Specifying a Loop Initiation interval (II) 5.2.4. Loop Concurrency (max_concurrency Pragma) 5.2.5. Specifying Work-Group Sizes 5.2.6. Specifying Number of Compute Units 5.2.7. Specifying Number of SIMD Work-Items
5.4. Implementing the Intel® FPGA SDK for OpenCL™ Standard Edition Channels Extension x
5.4.1. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition Channels Extension 5.4.2. Channel Data Behavior 5.4.3. Multiple Work-Item Ordering for Channels 5.4.4. Restrictions in the Implementation of Intel® FPGA SDK for OpenCL™ Standard Edition Channels Extension 5.4.5. Enabling the Intel® FPGA SDK for OpenCL™ Standard Edition Channels for OpenCL Kernel
5.4.3. Multiple Work-Item Ordering for Channels x
5.4.3.1. Work-Item Serial Execution of Channels
5.4.5. Enabling the Intel® FPGA SDK for OpenCL™ Standard Edition Channels for OpenCL Kernel x
5.4.5.1. Declaring the Channel Handle 5.4.5.2. Implementing Blocking Channel Writes 5.4.5.3. Implementing Blocking Channel Reads 5.4.5.4. Implementing I/O Channels Using the io Channels Attribute 5.4.5.5. Emulating I/O Channels 5.4.5.6. Use Models of Intel® FPGA SDK for OpenCL™ Standard Edition Channels Implementation 5.4.5.7. Implementing Buffered Channels Using the depth Channels Attribute 5.4.5.8. Enforcing the Order of Channel Calls
5.4.5.2. Implementing Blocking Channel Writes x
5.4.5.2.1. Implementing Nonblocking Channel Writes
5.4.5.3. Implementing Blocking Channel Reads x
5.4.5.3.1. Implementing Nonblocking Channel Reads
5.4.5.8. Enforcing the Order of Channel Calls x
5.4.5.8.1. Defining Memory Consistency Across Kernels When Using Channels
5.5. Implementing OpenCL Pipes x
5.5.1. Overview of the OpenCL Pipe Functions 5.5.2. Pipe Data Behavior 5.5.3. Multiple Work-Item Ordering for Pipes 5.5.4. Restrictions in OpenCL Pipes Implementation 5.5.5. Enabling OpenCL Pipes for Kernels 5.5.6. Direct Communication with Kernels via Host Pipes
5.5.3. Multiple Work-Item Ordering for Pipes x
5.5.3.1. Work-Item Serial Execution of Pipes
5.5.5. Enabling OpenCL Pipes for Kernels x
5.5.5.1. Ensuring Compatibility with Other OpenCL SDKs 5.5.5.2. Declaring the Pipe Handle 5.5.5.3. Implementing Pipe Writes 5.5.5.4. Implementing Pipe Reads 5.5.5.5. Implementing Buffered Pipes Using the depth Attribute 5.5.5.6. Implementing I/O Pipes Using the io Attribute 5.5.5.7. Enforcing the Order of Pipe Calls
5.5.5.7. Enforcing the Order of Pipe Calls x
5.5.5.7.1. Defining Memory Consistency Across Kernels When Using Pipes
5.5.6. Direct Communication with Kernels via Host Pipes x
5.5.6.1. Optional intel_host_accessible Kernel Argument Attribute 5.5.6.2. API Functions for Interacting with cl_mem Pipe Objects Bound to Host-Accessible Pipe Kernel Arguments 5.5.6.3. Creating a Host Accessible Pipe 5.5.6.4. Example Use of the cl_intel_fpga_host_pipe Extension
5.9. Including Structure Data Types as Arguments in OpenCL Kernels x
5.9.1. Matching Data Layouts of Host and Kernel Structure Data Types 5.9.2. Disabling Insertion of Data Structure Padding 5.9.3. Specifying the Alignment of a Struct
5.10. Inferring a Register x
5.10.1. Inferring a Shift Register
5.12. Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
5.12.1. Programming Strategies for Inferring the Accumulator
6. Designing Your Host Application x
6.1. Host Programming Requirements 6.2. Allocating OpenCL Buffers for Manual Partitioning of Global Memory 6.3. Collecting Profile Data During Kernel Execution 6.4. Accessing Custom Platform-Specific Functions 6.5. Modifying Host Program for Structure Parameter Conversion 6.6. Managing Host Application 6.7. Allocating Shared Memory for OpenCL Kernels Targeting SoCs 6.8. Debugging Your OpenCL System That is Gradually Slowing Down
6.1. Host Programming Requirements x
6.1.1. Host Machine Memory Requirements 6.1.2. Host Binary Requirement 6.1.3. Multiple Host Threads 6.1.4. Out-of-Order Command Queues 6.1.5. Requirement for Multiple Command Queues to Execute Kernels Concurrently
6.2. Allocating OpenCL Buffers for Manual Partitioning of Global Memory x
6.2.1. Partitioning Buffers Across Multiple Interfaces of the Same Memory Type 6.2.2. Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) 6.2.3. Creating a Pipe Object in Your Host Application
6.3. Collecting Profile Data During Kernel Execution x
6.3.1. Profiling Enqueued and Autorun Kernels 6.3.2. Profile Data Acquisition 6.3.3. Multiple Autorun Profiling Calls
6.6. Managing Host Application x
6.6.1. Displaying Example Makefile Fragments (example-makefile or makefile) 6.6.2. Compiling and Linking Your Host Application 6.6.3. Linking Your Host Application to the Khronos ICD Loader Library 6.6.4. Programming an FPGA via the Host 6.6.5. Termination of the Runtime Environment and Error Recovery
6.6.2. Compiling and Linking Your Host Application x
6.6.2.1. Displaying Flags for Compiling Host Application (compile-config) 6.6.2.2. Displaying Paths to OpenCL Host Runtime and MMD Libraries (ldflags) 6.6.2.3. Listing OpenCL Host Runtime and MMD Libraries (ldlibs) 6.6.2.4. Displaying Information on OpenCL Host Runtime and MMD Libraries (link-config or linkflags)
6.6.3. Linking Your Host Application to the Khronos ICD Loader Library x
6.6.3.1. Linking to the ICD Loader Library on Windows 6.6.3.2. Linking to the ICD Loader Library on Linux
6.6.4. Programming an FPGA via the Host x
6.6.4.1. Programming Multiple FPGA Devices
6.6.4.1. Programming Multiple FPGA Devices x
6.6.4.1.1. Probing the OpenCL FPGA Devices 6.6.4.1.2. Querying Device Information 6.6.4.1.3. Loading Kernels for Multiple FPGA Devices
7. Compiling Your OpenCL Kernel x
7.1. Compiling Your Kernel to Create Hardware Configuration File 7.2. Compiling Your Kernel without Building Hardware (-c) 7.3. Specifying the Location of Header Files (-I=<directory>) 7.4. Specifying the Name of an Intel® FPGA SDK for OpenCL™ Offline Compiler Output File (-o=<filename>) 7.5. Compiling a Kernel for a Specific FPGA Board (-board=<board_name>) 7.6. Resolving Hardware Generation Fitting Errors during Kernel Compilation (-high-effort) 7.7. Defining Preprocessor Macros to Specify Kernel Parameters (-D<macro_name>) 7.8. Generating Compilation Progress Report (-v) 7.9. Displaying the Estimated Resource Usage Summary On-Screen (-report) 7.10. Suppressing Warning Messages from the Intel® FPGA SDK for OpenCL™ Offline Compiler (-W) 7.11. Converting Warning Messages from the Intel® FPGA SDK for OpenCL™ Offline Compiler into Error Messages (-Werror) 7.12. Removing Debug Data from Compiler Reports and Source Code from the .aocx File (-g0) 7.13. Disabling Burst-Interleaving of Global Memory (-no-interleaving=<global_memory_type>) 7.14. Configuring Constant Memory Cache Size (-const-cache-bytes=<N>) 7.15. Relaxing the Order of Floating-Point Operations (-fp-relaxed) 7.16. Reducing Floating-Point Rounding Operations (-fpc)
8. Emulating and Debugging Your OpenCL Kernel x
8.1. Modifying Channels Kernel Code for Emulation 8.2. Compiling a Kernel for Emulation (-march=emulator) 8.3. Emulating Your OpenCL Kernel 8.4. Debugging Your OpenCL Kernel on Linux 8.5. Limitations of the Intel® FPGA SDK for OpenCL™ Standard Edition Emulator 8.6. Discrepancies in Hardware and Emulator Results
8.1. Modifying Channels Kernel Code for Emulation x
8.1.1. Emulating a Kernel that Passes Pipes or Channels by Reference 8.1.2. Emulating Channel Depth
10. Profiling Your OpenCL Kernel x
10.1. Instrumenting the Kernel Pipeline with Performance Counters (-profile) 10.2. Launching the Intel® FPGA Dynamic Profiler for OpenCL™ GUI (report) 10.3. Profiling Autorun Kernels
11. Developing OpenCL™ Applications Using Intel® Code Builder for OpenCL™ x
11.1. Configuring the Intel® Code Builder for OpenCL™ Offline Compiler Plug-in for Microsoft Visual Studio 11.2. Configuring the Intel® Code Builder for OpenCL™ Offline Compiler Plug-in for Eclipse 11.3. Creating a Session in the Intel® Code Builder for OpenCL™ 11.4. Configuring a Session
12. Intel® FPGA SDK for OpenCL™ Standard Edition Advanced Features x
12.1. OpenCL Library 12.2. Kernel Attributes for Configuring Local and Private Memory Systems 12.3. Kernel Attributes for Reducing the Overhead on Hardware Usage 12.4. Kernel Replication Using the num_compute_units(X,Y,Z) Attribute
12.1. OpenCL Library x
12.1.1. Understanding RTL Modules and the OpenCL Pipeline 12.1.2. Packaging an OpenCL Helper Function File for an OpenCL Library 12.1.3. Packaging an RTL Component for an OpenCL Library 12.1.4. Verifying the RTL Modules 12.1.5. Packaging Multiple Object Files into a Library File 12.1.6. Specifying an OpenCL Library when Compiling an OpenCL Kernel 12.1.7. Using an OpenCL Library that Works with Simple Functions (Example 1) 12.1.8. Using an OpenCL Library that Works with External Memory (Example 2) 12.1.9. OpenCL Library Command-Line Options
12.1.1. Understanding RTL Modules and the OpenCL Pipeline x
12.1.1.1. Overview: Intel FPGA SDK for OpenCL Pipeline Approach 12.1.1.2. Integration of an RTL Module into the Intel FPGA SDK for OpenCL Pipeline 12.1.1.3. Stall-Free RTL 12.1.1.4. RTL Module Interfaces 12.1.1.5. Avalon Streaming (Avalon-ST) Interface 12.1.1.6. RTL Reset and Clock Signals 12.1.1.7. XML Syntax of an RTL Module 12.1.1.8. Interaction between RTL Module and External Memory 12.1.1.9. Order of Threads Entering an RTL Module 12.1.1.10. OpenCL C Model of an RTL Module 12.1.1.11. Potential Incompatibility between RTL Modules and Partial Reconfiguration
12.1.1.7. XML Syntax of an RTL Module x
12.1.1.7.1. XML Elements for ATTRIBUTES 12.1.1.7.2. XML Elements for INTERFACE 12.1.1.7.3. XML Elements for RESOURCES
12.1.3. Packaging an RTL Component for an OpenCL Library x
12.1.3.1. Restrictions and Limitations in RTL Support for the Intel® FPGA SDK for OpenCL™ Standard Edition Library Feature
12.2. Kernel Attributes for Configuring Local and Private Memory Systems x
12.2.1. Restrictions on the Usage of Variable-Specific Attributes
12.3. Kernel Attributes for Reducing the Overhead on Hardware Usage x
12.3.1. Hardware for Kernel Interface
12.3.1. Hardware for Kernel Interface x
12.3.1.1. Omit Hardware that Generates and Dispatches Kernel IDs 12.3.1.2. Omit Communication Hardware between the Host and the Kernel
12.4. Kernel Replication Using the num_compute_units(X,Y,Z) Attribute x
12.4.1. Customization of Replicated Kernels Using the get_compute_id() Function 12.4.2. Using Channels with Kernel Copies
A. Support Statuses of OpenCL Features x
A.1. Support Statuses of OpenCL 1.0 Features A.2. Support Statuses of OpenCL 1.2 Features A.3. Support Statuses of OpenCL 2.0 Features A.4. Intel® FPGA SDK for OpenCL™ Standard Edition Allocation Limits
A.1. Support Statuses of OpenCL 1.0 Features x
A.1.1. OpenCL1.0 C Programming Language Implementation A.1.2. OpenCL C Programming Language Restrictions A.1.3. Argument Types for Built-in Geometric Functions A.1.4. Numerical Compliance Implementation A.1.5. Image Addressing and Filtering Implementation A.1.6. Atomic Functions A.1.7. Embedded Profile Implementation
A.2. Support Statuses of OpenCL 1.2 Features x
A.2.1. OpenCL 1.2 Runtime Implementation A.2.2. OpenCL 1.2 C Programming Language Implementation
A.3. Support Statuses of OpenCL 2.0 Features x
A.3.1. OpenCL 2.0 Headers A.3.2. OpenCL 2.0 Runtime Implementation A.3.3. OpenCL 2.0 C Programming Language Restrictions for Pipes
1. Intel® FPGA SDK for OpenCL™ Standard Edition Overview
2. Intel® FPGA SDK for OpenCL™ Offline Compiler Kernel Compilation Flows
3. Obtaining General Information on Software, Compiler, and Custom Platform
4. Managing an FPGA Board
5. Structuring Your OpenCL Kernel
6. Designing Your Host Application
7. Compiling Your OpenCL Kernel
8. Emulating and Debugging Your OpenCL Kernel
9. Reviewing Your Kernel's report.html File
10. Profiling Your OpenCL Kernel
11. Developing OpenCL™ Applications Using Intel® Code Builder for OpenCL™
12. Intel® FPGA SDK for OpenCL™ Standard Edition Advanced Features
A. Support Statuses of OpenCL Features
B. Document Revision History of the Intel® FPGA SDK for OpenCL™ Standard Edition Programming Guide

B. Document Revision History of the Intel® FPGA SDK for OpenCL™ Standard Edition Programming Guide

Document Version Intel® Quartus® Prime Version Changes
2019.04.22 18.1 Fixed broken links.
2018.09.24 18.1
  • Maintenance release
2018.05.04 18.0
  • Removed Intel® Quartus® Prime Pro Edition software-related information.
  • Under Programming Strategies for Optimizing Data Processing Efficiency, added the topic Loop Concurrency (max_concurrency Pragma).
  • Modified topic title Programming Strategies for Optimizing Local Memory Efficiency to Programming Strategies for Optimizing Pointer-to-Local Memory Size.
  • In Emulating I/O Channels, removed the section Emulating Communication Between a Kernel and a Host or Other Process (Linux only).
  • Modified the topic title Requirement for Multiple Command Queues in Channels or Pipes Implementation to Requirement for Multiple Command Queues to Execute Kernels Concurrently, and updated its content.
  • In Direct Communication wit Kernels via Host Pipes:
    • Retitled New Optional Kernel Argument Attribute to Optional intel_host_accessible Kernel Argument Attribute.
    • Retitled New API Functions to API Functions for Interacting with cl_mem Pipe Objects Bound to Host-Accessible Pipe Kernel Arguments.
  • In Intel® FPGA SDK for OpenCL™ Allocation Limits, removed reference to the environment variable CL_CONTEXT_PROGRAM_VARIABLES_TOTAL_SIZE_INTELFPGA because the runtime no longer supports it.
  • In XML Syntax of an RTL Module, added information on the RESOURCES element.
    • Added the topic XML Elements for RESOURCES.
Date Version Changes
December 2017 2017.12.08
  • Added the following new topics:
    • Profiling Autorun Kernels
    • Profiling Enqueued and Autorun Kernels
    • Profile Data Acquisition
    • Multiple Autorun Profiling Calls
    • Developing OpenCL Applications Using Intel Code Builder for OpenCL
    • Configuring the Intel Code Builder for OpenCL Offline Compiler Plugin for Microsoft Visual Studio
    • Configuring the Intel Code Builder for OpenCL Offline Compiler Plugin for Eclipse
    • Creating a Session in the Intel Code Builder for OpenCL
    • Configuring a Session
  • In XML Syntax of an RTL Module, removed <PARAMETER name="WIDTH" value="32"/> from the XML specification file.
November 2017 2017.11.06
  • Moved topics into separate chapters.
  • Rebranded references to the following:
    • The macro ALTERA_CL to INTELFPGA_CL.
    • The environment variable ALTERAOCLSDKROOT to INTELFPGAOCLSDKROOT.
    • The environment variable CL_CONTEXT_PROGRAM_VARIABLES_TOTAL_SIZE_ALTERA to CL_CONTEXT_PROGRAM_VARIABLES_TOTAL_SIZE_INTELFPGA
    • clGetExtensionFunctionAddress to clGetExtensionFunctionAddressIntelFPGA
    • The environment variable CL_CONTEXT_EMULATOR_DEVICE_ALTERA to CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA
    • write_channel_altera to write_channel_intel
    • write_channel_nb_altera to write_channel_nb_intel
    • CL_MEM_BANK to CL_CHANNEL
    • CL_MEM_BANK_1_INTEL to CL_CHANNEL_1_INTELFPGA
    • CL_MEM_BANK_2_INTEL to CL_CHANNEL_2_INTELFPGA
    • Arria 10 to Intel® Arria® 10
    • Quartus Prime to Intel Quartus Prime
    • Intel® FPGA SDK for OpenCL™ Profiler to Intel® FPGA dynamic profiler for OpenCL™
    • TimeQuest Timing Analyzer to Timing Analyzer
    • Qsys Pro to Platform Designer
  • In Intel FPGA SDK for OpenCL FPGA Programming Flow, added FPGA data flow architecture diagram and related text.
  • In Intel FPGA SDK for OpenCL Advanced Features section, added RTL Module Interfaces to provide example of how RTL module interfaces operate.
  • Updated the timing diagram in Avalon Streaming (Avalon-ST) Interface.
  • In Implementing Blocking Channel Writes and Implementing Blocking Channel Reads, removed "which cannot be a constant" in the definition of <type>.
  • Added the topic Debugging Your OpenCL System That is Gradually Slowing Down.
  • Added a link to PLDA website in Compiling Your OpenCL Kernel.
  • Updated the last bullet point of Guidelines for Naming the Kernel to include the keywords VHDL and Verilog.
  • In Intel FPGA SDK for OpenCL Advanced Features, listed the aspects of the design that can be controlled.
  • In OpenCL Library, added the expansion of RTL.
  • Split the sections of Understanding RTL Modules and the OpenCL Pipeline into individual topics Overview: Intel FPGA SDK for OpenCL Pipeline Approach and Integration of an RTL Module into the Intel FPGA SDK for OpenCL Pipeline.
  • In Overview: Intel FPGA SDK for OpenCL Pipeline Approach, aligned the left-hand example code with image on the right-hand. Moved the bottom portion of the image above the paragraph, which explains the image.
  • In Integration of an RTL Module into the Intel FPGA SDK for OpenCL Pipeline, added related links about Avalon™ -ST.
  • In Stall-Free RTL, split the paragraph into steps and added related links.
  • In Requirements for Deterministic Multiple Work-Item Ordering, added a third requirement for work-item ordering.
  • Updated Implementing Nonblocking Channel Reads.
  • Added new topicSpeeding Up Your OpenCL Compilation (-fast-compile) and implemented the convention -option=<value>.
  • In One-Step Compilation for Simple Kernels and Multistep Intel FPGA SDK for OpenCL Design Flow, replaced references to .log file with HTML report and double dash command option with single dash.
  • In Compiling a Kernel for Emulation (-march=emulator), added support for Stratix 10
  • InObtaining General Information on Software, Compiler, and Custom Platform, added a Notice to highlight that double dash and -option <value> conventions of aoc command are deprecated.
  • Implemented the conventions single dash and -option=<value> in the following topics:
    • Displaying the Compiler Version (-version)
    • Listing the Intel FPGA SDK for OpenCL Offline Compiler Command Options (no argument, -help, or -h)
    • Listing the Available FPGA Boards in Your Custom Platform (-listboards)
    • Partitioning Buffers Across Multiple Interfaces of the Same Memory Type
    • Specifying the Location of Header Files (-I=<directory>)
    • Specifying the Name of an Intel FPGA SDK for OpenCL Offline Compiler Output File (-o=<filename>)
    • Compiling a Kernel for a Specific FPGA Board (-board=<board_name>)
    • Resolving Hardware Generation Fitting Errors during Kernel Compilation (-high-effort)
    • Defining Preprocessor Macros to Specify Kernel Parameters (-D<macro_name>)
    • Displaying the Estimated Resource Usage Summary On-Screen (-report)
    • Disabling Burst-Interleaving of Global Memory (-no-interleaving=<global_memory_type>)
    • Configuring Constant Memory Cache Size (-const-cache-bytes=<N>)
    • Relaxing the Order of Floating-Point Operations (-fp-relaxed)
    • Reducing Floating-Point Rounding Operations (-fpc)
    • Emulating Channel Depth
    • Compiling a Kernel for Emulation (-march=emulator)
    • Packaging an OpenCL Helper Function File for an OpenCL Library
    • OpenCL Library Command-Line Options
    • Instrumenting the Kernel Pipeline with Performance Counters (-profile)
  • In Accessing Custom Platform-Specific Functions, added related links to ICD loader.
  • In Specifying Number of Compute Units, Kernel Replication Using the num_compute_units(X,Y,Z) Attribute, and Emulating Your OpenCL Kernel, added a note on compute unit.
  • In Compiling a Kernel for Emulation (-march=emulator), added support for Intel Stratix 10.
  • Added a new topic Discrepancies in Hardware and Emulator Results.
  • Added support status column legend OpenCL C Programming Language Restrictions
  • Simplified the flowcharts in One-Step Compilation for Simple Kernels and Multistep Intel FPGA SDK for OpenCL Design Flow and updated the texts relevantly.
  • Removed references to AOCL_BOARD_PACKAGE_ROOT throughout the guide since it is deprecated.
  • Updated instances of aocl install to aocl install <path_to_customplatform>.
  • Updated instances of aocl uninstall to aocl uninstall <path_to_customplatform>
  • Added the following new topics for host pipes:
    • Direct Communication with Kernels via Host Pipes
    • Optional intel_host_accessible Kernel Argument Attribute
    • API Functions for Interacting with cl_mem Pipe Objects Bound to Host-Accessible Pipe Kernel Arguments
    • Creating a Host Accessible Pipe
    • Example Use of the cl_intel_fpga_host_pipe Extension
  • In Enabling the Intel FPGA SDK for OpenCL Channels for OpenCL Kernel, added the pragma to enable the channel extension.
  • Updated the design example compilation procedures in Using an OpenCL Library that Works with Simple Functions (Example 1) and Using an OpenCL Library that Works with External Memory (Example 2).
  • In Restrictions in the Implementation of Intel FPGA SDK for OpenCL Channels Extension, replaced the Single Site call sub-section with Multiple Channel Call Site.
May 2017 2017.05.08
  • Rebranded some functions in code examples as follows:
    • Rebranded read_channel_altera to read_channel_intel.
    • Rebranded write_channel_altera to write_channel_intel.
    • Rebranded read_channel_nb_altera to read_channel_nb_intel.
    • Rebranded write_channel_nb_altera to write_channel_nb_intel.
    • Rebranded clGetBoardExtensionFunctionAddressAltera to clGetBoardExtensionFunctionAddressIntelFPGA.
  • Added Emulating I/O Channels.
  • Added Implementing Arbitrary Precision Integers.
  • Added Coalescing Nested Loops.
  • Added Specifying a Loop Initiation Interval (II).
  • Added Emulating Channel Path.
  • Added Avalon Streaming (Avalon-ST) Interface.
  • Removed all references to #pragma OPENCL EXTENSION cl_altera_channels : enable because this pragma is not required to implement channels.
  • Reorganized information related to heterogeneous memory as follows:
    • Merged Specifying Pointer Size in Memory content into Programming Strategies for Optimizing Local Memory Efficiency.
    • Restructured into three topics:
      • Allocating OpenCL Buffers for Manual Partitioning of Global Memory
      • Partitioning Buffers Across Multiple Interfaces of the Same Memory Type
      • Partitioning Buffers Across Different Memory Types (Heterogeneous Memory)
    • Moved Specifying Buffer Location in Global Memory (previously under Programming Strategies for Optimizing Access Efficiency) content into Partitioning Buffers Across Different Memory Types (Heterogeneous Memory).
  • Updated Collecting Profile Data During Kernel Execution with a warning about the affect of collecting profile data on kernel launch times.
  • Updated Compiling Your OpenCL Kernel with restrictions on compiling an encrypted .cl file.
  • Updated Restrictions and Limitations in RTL Support for the Library Feature to indicate that an RTL module must use a single-input Avalon-ST interface to control inputs.
  • Updated topics affected by changes to the OpenCL profiler as follows:
    • Updated Launching the GUI (report) with new command options.
    • Updated the figure Multistep Intel® FPGA SDK for OpenCL™ Design Flow in the topic Multistep Intel® FPGA SDK for OpenCL™ Design Flow to reflect the new command options.
  • Corrected code example in Implementing Nonblocking Channel Reads.
  • Corrected code example in Channel Execution in Loop with Multiple Work-Items section of Work-Item Serial Execution of Channels.
  • In Intel FPGA SDK for OpenCL Advanced Features section, made the following updates:
    • Updated Interaction between RTL Module and External Memory to indicate preferred method for RTL module and external memory interactions.
    • Updated Potential Incompatibility between RTL Modules and Partial Reconfiguration to include link to the partial reconfiguration guidelines in the Quartus Prime Pro Edition Handbook.
    • Added information about bankbits and mergeAllocating OpenCL Buffer for Manual Partitioning of kernel attributes to Kernel Attributes for Configuring Local and Private Memory Systems.
    • Rebranded some functions in code examples as follows:
      • Rebranded read_channel_altera to read_channel_intel.
      • Rebranded write_channel_altera to write_channel_intel.
October 2016 2016.10.31
  • Rebranded the Altera SDK for OpenCL to Intel® FPGA SDK for OpenCL™ .
  • Rebranded the Altera Offline Compiler to Intel® FPGA SDK for OpenCL™ Offline Compiler.
  • Deprecated and removed support for big-endian system, resulting in the following documentation changes:
    • Removed the topic Compiling a Kernel for a Big-Endian System (--big-endian).
    • Removed big-endian (64-bit) from the list of architectures that the host application can target.
  • Added the topic Displaying the Compilation Environment of an OpenCL Binary to introduce the aoc env command.
  • Removed Adding Source References to Optimization Reports (-g) because the offline compiler automatically includes source information in the compiler reports and enables symbolic debug during emulation on an x86 Linux machine.
  • Added the topic Removing Debug Data from Compiler Reports and Source Code from the .aocx File (-g0) to introduce the -g0 aoc command option.
  • In Limitations of the Intel® FPGA SDK for OpenCL™ Emulator, removed the limitation "The Emulator does not support half data type".
  • In Linking Your Host Application to the Khronos ICD Loader Library, provided an update that the Intel® -supplied ICD Loader Library supports OpenCL Specification version 1.0 as well as implemented APIs from the OpenCL Specification versions 1.1, 1.2, and 2.0.
  • In Managing an FPGA Board, provided the following updates:
    • Noted that the SDK supports installation of multiple Custom Platforms. To use the SDK utilities on each board in a multi-board installation, the AOCL_BOARD_PACKAGE_ROOT environment variable setting must correspond to the Custom Platform subdirectory of the associated board.
    • Noted that in a system with multiple Custom Platforms, the host program should use ACD to discover the boards instead of directly linking to the MMD libraries.
  • Added the topic Reviewing Your Kernel's report.html File and included deprecation notice for the analyze-area utility option. As a result of introducing the HTML report, removed the following topics:
    • Reviewing Your Kernel's Resource Usage Information in the Area Report
    • Accessing the Area Report
    • Layout of the Area Report
  • In Multistep Design Flow, updated the design steps and the figure The Multistep Intel® FPGA SDK for OpenCL™ Design Flow to replace area report with the HTML report, and remove information on enabling -g.
  • In Inferring a Register, corrected the text following the code snippet that explained how the offline compiler decide on the implementation of the array in hardware.
  • In Linking to the ICD Loader Library on Windows, updated the text to improve clarity.
  • In Support Statuses of OpenCL Features section, made the following updates:
    • Rebranded the Altera SDK for OpenCL to Intel® FPGA SDK for OpenCL™ .
    • Rebranded the Altera Offline Compiler to Intel® FPGA SDK for OpenCL™ Offline Compiler.
    • Modified information in the Intel® FPGA SDK for OpenCL™ Allocation Limits section:
      • Updated information regarding minimum global memory allocation by runtime.
      • Updated the maximum number of queues from 70 to 256.
      • Updated the maximum number of kernels per FPGA device from 64 to no static limit when compiling to hardware and 256 when compiling to emulator.
    • In OpenCL 1.0 C Programming Language Implementation, under the Description column for half-precision float, added a note that this feature is supported in the Emulator. In addition, updated the support status of half-precision float from X to ○.
    • Under Support Statuses of OpenCL 2.0 Features, added the topic OpenCL 2.0 Headers to explain that using the OpenCL 2.0 headers to call unsupported APIs will result in an error.
May 2016 2016.05.02
  • Added a schematic diagram of the AOCL programming model in the Altera SDK for OpenCL FPGA Programming Flow section.
  • Moved the figure The AOCL FPGA Programming Flow to the Altera Offline Compiler Kernel Compilation Flows section.
  • Updated the figure The Multistep AOCL Design Flow and associated text to include the Review Area Report step.
  • Added information on the single-cycle floating-point accumulator feature for single work-item kernels. Refer to the Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels section for more information.
  • Added information in the Emulating Your OpenCL Kernel section on multi-device support for emulation alongside other OpenCL SDKs using ICD.
  • Included information on the enhanced area report feature:
    • Added the option to invoke the analyze-area AOCL utility command to generate an HTML area report.
    • Included a topic that describes the layout of the HTML area report.
  • In Linking to the ICD Loader Library on Windows, removed $(AOCL_LDLIBS) from the code example for the modified Makefile.
  • In the Multiple Work-Item Ordering sections for channels and pipes, modified the characteristics that the AOCL uses to check whether the channel or pipe call is work-item invariant.
  • Added Altera SDK for OpenCL Advanced Feature section.
  • In OpenCL 1.2 Runtime Implementation under Support Statuses of OpenCL Features sections, noted that AOCL supports the clSetEventCallback, clGetKernelArgInfo, and clSetMemObjectDestructorCallback APIs.
November 2015 2015.11.02
  • Added the option to invoke the aoc command with no argument to access the Altera Offline Compiler help menu.
  • Updated the Multiple Host Threads section to specify that the OpenCL™ host runtime is thread-safe.
  • Updated the following figure and sections to reflect multiple kernel source file support:
    • The figure The AOCL FPGA Programming Flow in the AOCL FPGA Programming Flow section
    • The Compiling Your Kernel to Create Hardware Configuration File section
    • The Compiling Your Kernel without Building Hardware (-c) section
  • In Multiple Work-Item Ordering for Channels, removed misleading text.
  • Updated the Overview of Channels Implementation figure.
  • Updated the following sections on OpenCL pipes:
    • Overview of a Pipe Network Implementation figure in Overview of the OpenCL Pipe Functions
    • Emulation support in Restrictions in OpenCL Pipes Implementation section
    • Replaced erroneous code with the correct syntax
    • Added link to Implementing I/O Pipes Using the io Attribute in Declaring the Pipe Handle
  • Added a reminder in Programming an FPGA via the Host that you should release an event object after use to prevent excessive memory usage.
  • In Support Statuses of OpenCL Features section, made the following updates:
    • Categorized feature support statuses and limitations based on OpenCL Specification versions.
    • Added the following functions to the list of OpenCL-conformant double precision floating-point functions:

      sinh / cosh / tanh / asinh / acosh / atanh / pow / pown / powr / tanh / atan / atan2 / ldexp / log1p / sincos

    • In OpenCL 1.2 Runtime Implementation, added sub-buffer object support.
    • In OpenCL 2.0 Runtime Implementation, added preliminary shared virtual memory support.
    • In Altera SDK for OpenCL Allocation Limits, added a minimum global memory allocation limit by the runtime.
May 2015 15.0.0
  • In Guidelines for Naming the Kernel, added entry that advised against naming an OpenCL kernel kernel.cl.
  • In Instrumenting the Kernel Pipeline with Performance Counters (--profile), specified that you should run the host application from a local disk to avoid potential delays caused by slow network disk accesses.
  • In Emulating and Debugging Your OpenCL Kernel, modified Caution note to indicate that you must emulate a design targeting an SoC on a non-SoC board.
  • In Emulating Your OpenCL Kernel, updated command to run the host application and added instruction for overriding default temporary directory containing <process_ID>-libkernel.so.
  • Introduced the --high-effort aoc command flag in Resolving Hardware Generation Fitting Errors during Kernel Compilation.
  • In Enabling Double Precision Floating-Point Operations, introduced the OPENCL EXTENSION pragma for enabling double precision floating-point operations.
  • Introduced OpenCL pipes support. Refer to Implementing OpenCL Pipes (and subsequent subtopics) and Creating a Pipe Object in Your Host Application for more information.
  • In AOCL Channels Extension: Restrictions, added code examples to demonstrate how to statically index into arrays of channel IDs.
  • In Multiple Host Threads, added recommendation for synchronizing OpenCL host function calls in a multi-threaded host application.
  • Introduced ICD and ACD support. Refer to Linking Your Host Application to the Khronos ICD Loader Library for more information.
  • Introduced clGetBoardExtensionFunctionAddressAltera for referencing user-accessible functions. Refer to Accessing Custom Platform-Specific Functions for more information.
  • In Support Statuses of OpenCL Features section, made the following updates:
    • Listed the double precision floating-point functions that the Altera® SDK for OpenCL™ supports preliminarily.
    • Added OpenCL C Programming Language Restrictions for Pipes.
December 2014 14.1.0
  • Reorganized information flow. Information is now presented based on the tasks you might perform using the Altera® SDK for OpenCL™ (AOCL) or the Altera RTE for OpenCL.
  • Removed information pertaining to the --util <N> and -O3 Altera Offline Compiler (AOC) options.
  • Added the following information on PLDA QuickUDP IP core licensing in Compiling Your OpenCL Kernel:
    1. A PLDA QuickUDP IP core license is required for the Stratix® V Network Reference Platform or a Custom Platform that uses the QuickUDP IP core.
    2. Improper installation of the QuickUDP IP core license causes compilation to fail with an error message that refers to the QuickTCP IP core.
  • Added reminder that conditionally shifting a large shift register is not recommended.
  • Removed the Emulating Systems with Multiple Devices section. A new env CL_CONTEXT_EMULATOR_DEVICE_ALTERA=<number_of_devices> command is now available for emulating multiple devices.
  • Removed language support limitation from the Limitations of the AOCL Emulator section.
  • In AOCL Allocation Limits under Support Statuses of OpenCL Features section, updated the maximum number of kernels per FPGA device from 32 to 64.
June 2014 14.0.0
  • Removed the --estimate-throughput and --sw-dimm-partition AOC options
  • Added the -march=emulator, -g, --big-endian, and --profile AOC options
  • --no-interleaving needs <global_memory_type> argument
  • -fp-relaxed=true is now --fp-relaxed
  • -fpc=true is now --fpc
  • For non-SoC devices, aocl diagnostic is now aocl diagnose and aocl diagnose <device_name>
  • program and flash need <device_name> arguments
  • Added Identifying the Device Name of Your FPGA Board
  • Added AOCL Profiler Utility
  • Added AOCL Channels Extension and associated subsections
  • Added Attributes for Channels
  • Added Match Data Layouts of Host and Kernel Structure Data Types
  • Added Register Inference and Shift Register Inference
  • Added Channels and Multiple Command Queues
  • Added Shared Memory Accesses for OpenCL Kernels Running on SoCs
  • Added Collecting Profile Data During Kernel Execution
  • Added Emulate and Debug Your OpenCL Kernel and associated subsections
  • Updated AOC Kernel Compilation Flows
  • Updated -v
  • Updated Host Binary Requirement
  • Combined Partitioning Global Memory Accesses and Partitioning Heterogeneous Global Memory Accesses into the section Partitioning Global Memory Accesses
  • Updated AOC Allocation Limits in Appendix A
  • Removed max_unroll_loops, max_share_resources, num_share_resources, and task kernel attributes
  • Added packed, and aligned(<N>) kernel attributes
  • In Support Statuses of OpenCL Features section, updated the following AOCL allocation limits:
    • Maximum number of contexts
    • Maximum number of queues
    • Maximum number of even objects per context
December 2013 13.1.1
  • Removed the section -W and -Werror, and replaced it with two sections: -W and -Werror.
  • Updated the following contents to reflect multiple devices support:
    • The figure The AOCL FPGA Programming Flow.
    • --list-boards section.
    • -board <board_name> section.
    • section.
    • Added the subsection Programming Multiple FPGA Devices under FPGA Programming.
  • The following contents were added to reflect heterogeneous global memory support:
    • --no-interleaving section.
    • buffer_location kernel attribute under Kernel Pragmas and Attributes.
    • Partitioning Heterogeneous Global Memory Accesses section.
  • Modified support status designations in Appendix: Support Statuses of OpenCL Features.
  • Removed information on OpenCL programming language restrictions from the section OpenCL Programming Language Implementation, and presented the information in a new section titled OpenCL Programming Language Restrictions.
November 2013 13.1.0
  • Reorganized information flow.
  • Updated and renamed Intel® FPGA SDK for OpenCL™ Compilation Flow to AOCL FPGA Programming Flow.
  • Added figures One-Step AOC Compilation Flow and Two-Step AOC Compilation Flow.
  • Updated the section Contents of the AOCL Version 13.1.
  • Removed the following sections:
    • OpenCL Kernel Source File Compilation.
    • Using the Altera Offline Kernel Compiler.
    • Setting Up Your FPGA Board.
    • Targeting a Specific FPGA Board.
    • Running Your OpenCL Application.
    • Consolidating Your Kernel Source Files.
    • Aligned Memory Allocation.
    • Programming the FPGA Hardware.
    • Programming the Flash Memory of an FPGA.
  • Updated and renamed Compiling the OpenCL Kernel Source File to AOC Compilation Flows.
  • Renamed Passing File Scope Structures to OpenCL Kernels to Use Structure Arguments in OpenCL Kernels.
  • Updated and renamed Augmenting Your OpenCL Kernel by Specifying Kernel Attributes and Pragmas to Kernel Pragmas and Attributes.
  • Renamed Loading Kernels onto an FPGA to FPGA Programming.
  • Consolidated Compiling and Linking Your Host Program, Host Program Compilation Settings, and Library Paths and Links into a single section.
  • Inserted the section Preprocessor Macros.
  • Renamed Optimizing Global Memory Accesses to Partitioning Global Memory Accesses.
June 2013 13.0 SP1.0
  • Added the section Setting Up Your FPGA Board.
  • Removed the subsection Specifying a Target FPGA Board under Kernel Programming Considerations.
  • Inserted the subsections Targeting a Specific FPGA Board and Generating Compilation Reports under Compiling the OpenCL Kernel Source File.
  • Renamed File Scope __constant Address Space Qualifier to __constant Address Space Qualifiers, and inserted the following subsections:
    • Function Scope __constant Variables.
    • File Scope __constant Variables.
    • Points to __constant Parameters from the Host.
  • Inserted the subsection Passing File Scope Structures to OpenCL Kernels under Kernel Programming Considerations.
  • Renamed Modifying Your OpenCL Kernel by Specifying Kernel Attributes and Pragmas to Augmenting Your OpenCL Kernel by Specifying Kernel Attributes and Pragmas.
  • Updated content for the unroll pragma directive in the section Augmenting Your OpenCL Kernel by Specifying Kernel Attributes and Pragmas.
  • Inserted the subsections Out-of-Order Command Queues and Modifying Host Program for Structure Parameter Conversion under Host Programming Considerations.
  • Updated the sections Loading Kernels onto an FPGA Using clCreateProgramWithBinary and Aligned Memory Allocation.
  • Updated flash programming instructions.
  • Renamed Optional Extensions in Appendix B to Atomic Functions, and updated its content.
  • Removed Platform Layer and Runtime Implementation from Appendix B.
May 2013 13.0.1
  • Explicit memory fence functions are now supported; the entry is removed from the table OpenCL Programming Language Implementation.
  • Updated the section Programming the Flash Memory of an FPGA.
  • Added the section Modifying Your OpenCL Kernel by Specifying Kernel Attributes and Pragmas to introduce kernel attributes and pragmas that can be implemented to optimize kernel performance.
  • Added the section Optimizing Global Memory Accesses to discuss data partitioning.
  • Removed the section Programming the FPGA with the aocl program Command from Appendix A.
May 2013 13.0.0
  • Updated compilation flow.
  • Updated kernel compiler commands.
  • Included Altera® SDK for OpenCL™ Utility commands.
  • Added the section OpenCL Programming Considerations.
  • Updated flash programming procedure and moved it to Appendix A.
  • Included a new clCreateProgramWithBinary FPGA hardware programming flow.
  • Moved the hostless clCreateProgramWithBinary hardware programming flow to Appendix A under the title Programming the FPGA with the aocl program Command.
  • Moved updated information on allocation limits and OpenCL language support to Appendix B.
November 2012 12.1.0 Initial release.
Level Two Title