Intel® FPGA SDK for OpenCL™ Standard Edition: Programming Guide

ID 683342
Date 4/22/2019
Document Table of Contents Avalon Streaming (Avalon-ST) Interface

The offline compiler expects the RTL module to support Avalon-ST interface with readyLatency = 0, at both input and output.

As shown in Integration of an RTL Module into an Intel FPGA SDK for OpenCL Pipeline, the RTL module must have 4 ports:
  • ivalid and iready, as the input Avalon-ST interface
  • ovalid and oready, as the output Avalon-ST interface
The following figure shows the timing diagram for input data transfer with back pressure. For more information about Avalon-ST interfaces, see the " Avalon Streaming Interfaces " section in Avalon Interface Specifications.

For an RTL module with a fixed latency, the output signals (ovalid and oready) can have constant high values, and the input ready signal (iready) can be ignored.

A stall-free RTL module might receive an invalid input signal (ivalid is low). In this case, the module ignores the input and produces invalid data on the output. For a stall-free RTL module without an internal state, it might be easier to propagate the invalid input through the module. However, for an RTL module with an internal state, you must handle an ivalid = 0 input carefully.