Arria 10 SoC Virtual Platform User Guide

ID 683326
Date 9/16/2015
Document Table of Contents

1.2. Arria 10 SoC Virtual Platform Block Diagram

The figure below details the Arria® 10 SoC device. Modules that are modeled in the Arria® 10 SoC Virtual Platform are highlighted in yellow in the diagram.

Figure 1. Arria 10 SoC Virtual Platform Block Diagram
Note: The System Manager and Clock Manager module are currently modeled after the Arria® V SoC device System Manager and Clock Manager register sets, respectively.
Table 1.  Modules Modeled in Arria 10 SoC Virtual Platform
Module Description
Dual ARM® Cortex® -A9 MPCore™ processor Contains two Cortex® -A9 with FPU support and a snoop control unit (SCU)
ARM® L2 Cache (PL310) 512 KB of shared, unified cache memory
General Interrupt Controller (GIC) Provides partial support for the interrupt map
System Interconnect (Arteris™ FlexNOC® network-on-chip (NoC))

Consists of the following:

  • Main level 3 (L3) interconnect
  • SDRAM L3 interconnect
  • Level 4 (L4) buses
Memory modules
  • Boot ROM
  • On-Chip RAM
Two 16550-compatible UARTs Each UART can interact with separate consoles
Four of the I2C controllers Four of the five I2C controllers in the Arria 10 SoC are modeled and two of the controllers can optionally be used for Ethernet PHY communication
Two Ethernet controllers Two of the three Ethernet controllers are modeled in the virtual platform
Two USB 2.0 OTG controllers Both USBs provide support for mass storage
Note: The USB controllers have been verified to work with the following USB storage devices:
  • PQI Cool Drive 350, up to 2GB
  • Apacer 4GB
  • Silicon Power 4GB
  • Pretec I-Disk 512MB
Two SPI master controllers and two slave controllers Supports full and half-duplex mode
Quad SPI flash controller Used for access to serial NOR flash devices
SD/MMC controller Used for interfacing to external SD and MMC flash cards and secure digital I/O devices
Clock Manager 1 Provides software-programmable clock control to configure all clocks generated in the HPS
System Manager1 Contains logic and registers to control system functions and other modules that need external control signals as part of their system integration
Reset Manager Generates module reset signals based on reset requests from the various sources in the HPS and FPGA fabric, and software writing to the module-reset control registers
DMA Provides high-bandwidth data transfers for modules without integrated DMA controllers. The DMA controller is based on the ARM® Corelink DMA Controller (DMA-330)
FPGA Manager Manages and monitors the FPGA portion of the System on a Chip (SoC) FPGA device
Four Timers General purpose timers are connected to the level 4 (L4) peripheral bus
Three GPIO Modules General purpose I/O interfaces
FPGA-to-HPS Bridge Provides access to the peripherals and memory in the HPS
HPS-to- FPGA Bridge Provides a configurable-width, high-performance master interface to the FPGA fabric
Lightweight HPS-to-FPGA Bridge Provides a lower-performance interface to the FPGA fabric
For more details on modeling aspects of the Arria 10 SoC Virtual Platform, refer to "Appendix B: Memory and Interrupt Maps."
1 This module's register set is modeled after the Arria® V SoC device.