OpenCL* Quick Start User Guide: Intel FPGA Programmable Acceleration Card D5005

Download
ID 683324
Date 7/21/2020
Public

1.3. Acronyms

Table 3.  Acronyms

Acronyms

Expansion

Description

AFU

Accelerator Functional Unit

Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance.

AF

Accelerator Function

Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application.

API

Application Programming Interface

A set of subroutine definitions, protocols, and tools for building software applications.

FIM

FPGA Interface Manager

The FPGA hardware containing the FPGA Interface Unit (FIU) and external interfaces for memory, networking, etc.

The Accelerator Function (AF) interfaces with the FIM at run time.

OPAE

Open Programmable Acceleration Engine

The OPAE is a software framework for managing and accessing AFs. 

RoT Root of Trust A source that can be trusted, such as the BMC in the Intel® FPGA PAC.
BSP Board Support Package A typical Intel® FPGA PAC BSP consists of software layers and a hardware project created using the Intel® Quartus® Prime Pro Edition software that Intel® FPGA SDK for OpenCL* compiler stitches accelerator code into and compiles. The BSP resides in the AFU.

Did you find the information on this page useful?

Characters remaining:

Feedback Message