Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 12/13/2021
Public

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Document Table of Contents

SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED

Disables setup and hold time violations detection in input registers of bi-directional pins.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Syntax


set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED <value>

Default Value

Off