1.7. Test Result Comments
In each test case, the RX JESD204C Intel® FPGA IP successfully establishes the sync header alignment, extended multiblock alignment, and until user data phase.
No data integrity issue is observed by the ramp checker for JESD configurations at different lanes rates covering all physical lanes, also no cyclic redundancy check (CRC) and command parity error is observed.
In the deterministic latency measurement, consistent RBD count and total latency between the TMSTP input of the ADC and the JESD Intel® FPGA IP transport layer output are observed across multiple power cycles or resets.
The modes LMF 881 and 661 are not valid ADC operation modes supported by the ADC12DJ5200RF device but are JESD204C ramp test pattern modes used to test all the physical lanes involved at different lane rates for data integrity errors.
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