AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

Download PDF
ID 683185
Date 6/09/2020
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. ADC12DJxx00RF EVM Software and JESD204C Example Design Setup 1.4. Hardware Checkout Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices 1.9. Appendix
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment 1.4.1.2. Extended Multiblock Alignment
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

1.6. Test Results

The following table contains the possible results and their definition.

Table 6.  Results Definition
Result Definition
PASS The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included (example: due to time limitations, only a portion of the testing was performed).
FAIL The DUT was observed to exhibit non-conformant behavior.
Warning The DUT was observed to exhibit behavior that is not recommended.
Refer to comments From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1/TL.2/TL.3, and TL.4 with different values of L, M, F, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 7.  Result for Test Cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1/TL.2/TL.3, and TL.4
Test No. L M F Data Rate

(Gbps)

 ADC Sampling Clock

(MHz)

 Link Clock

(MHz)

 Result
1 8 2 8 9.9 3000 75.00 PASS
2 6 1 2 10.3125 2500 78.125 PASS
3 6 2 2 10.3125 2500 78.125 PASS
4 4 1 1 10.3125 2500 78.125 PASS
5 4 2 1 10.3125 2500 78.125 PASS
6 4 2 2 10.3125 2500 78.125 PASS
7 4 4 2 10.3125 2500 78.125 PASS
8 2 2 2 10.3125 2500 78.125 PASS
9 2 4 4 10.3125 2500 78.125 PASS
10 8 8 1 9.9 3000 75.00 PASS
11 6 6 1 10.3125 2500 78.125 PASS
12 8 2 8 17.16 5200 130.00 PASS
13 6 1 2 16.5 4000 125.00 PASS
14 6 2 2 16.5 4000 125.00 PASS
15 4 1 1 16.5 4000 125.00 PASS
16 4 2 1 16.5 4000 125.00 PASS
17 4 2 2 16.5 4000 125.00 PASS
18 4 4 2 16.5 4000 125.00 PASS
19 2 2 2 16.5 4000 125.00 PASS
20 2 4 4 16.5 4000 125.00 PASS
21 8 8 1 17.16 5200 130.00 PASS
22 6 6 1 16.5 4000 125.00 PASS

The following table shows the results for test cases DL.1, DL.2, and DL.3 with different values of L, M, F, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 8.  Result for Deterministic Latency Test
Test L M F Data Rate (Gbps) ADC Sampling Clock (MHz) Link Clock (MHz) Result RBD Count Link Clock Latency Cycles
DL.1 8 2 8 9.9 3000 75.00 PASS 4 29
DL.2 8 2 8 9.9 3000 75.00 PASS
DL.3 8 2 8 9.9 3000 75.00 PASS
DL.1 6 1 2 10.3125 2500 78.125 PASS 4 30
DL.2 6 1 2 10.3125 2500 78.125 PASS
DL.3 6 1 2 10.3125 2500 78.125 PASS
DL.1 6 2 2 10.3125 2500 78.125 PASS 4 30
DL.2 6 2 2 10.3125 2500 78.125 PASS
DL.3 6 2 2 10.3125 2500 78.125 PASS
DL.1 4 1 1 10.3125 2500 78.125 PASS 4 30
DL.2 4 1 1 10.3125 2500 78.125 PASS
DL.3 4 1 1 10.3125 2500 78.125 PASS
DL.1 4 2 1 10.3125 2500 78.125 PASS 4 30
DL.2 4 2 1 10.3125 2500 78.125 PASS
DL.3 4 2 1 10.3125 2500 78.125 PASS
DL.1 4 2 2 10.3125 2500 78.125 PASS 4 N/A 10
DL.2 4 2 2 10.3125 2500 78.125 PASS
DL.1 4 4 2 10.3125 2500 78.125 PASS 4 N/A10
DL.2 4 4 2 10.3125 2500 78.125 PASS
DL.1 2 2 2 10.3125 2500 78.125 PASS 4 N/A10
DL.2 2 2 2 10.3125 2500 78.125 PASS
DL.1 2 4 4 10.3125 2500 78.125 PASS 4 N/A10
DL.2 2 4 4 10.3125 2500 78.125 PASS
DL.1 8 8 1 9.9 3000 75.00 PASS 4 N/A10
DL.2 8 8 1 9.9 3000 75.00 PASS
DL.1 6 6 1 10.3125 2500 78.125 PASS 4 N/A10
DL.2 6 6 1 10.3125 2500 78.125 PASS
DL.1 8 2 8 17.16 5200 130.00 PASS 5 30
DL.2 8 2 8 17.16 5200 130.00 PASS
DL.3 8 2 8 17.16 5200 130.00 PASS
DL.1 6 1 2 16.5 4000 125.00 PASS 5 30
DL.2 6 1 2 16.5 4000 125.00 PASS
DL.3 6 1 2 16.5 4000 125.00 PASS
DL.1 6 2 2 16.5 4000 125.00 PASS 5 30
DL.2 6 2 2 16.5 4000 125.00 PASS
DL.3 6 2 2 16.5 4000 125.00 PASS
DL.1 4 1 1 16.5 4000 125.00 PASS 5 30
DL.2 4 1 1 16.5 4000 125.00 PASS
DL.3 4 1 1 16.5 4000 125.00 PASS
DL.1 4 2 1 16.5 4000 125.00 PASS 5 31
DL.2 4 2 1 16.5 4000 125.00 PASS
DL.3 4 2 1 16.5 4000 125.00 PASS
DL.1 4 2 2 16.5 4000 125.00 PASS 5 N/A10
DL.2 4 2 2 16.5 4000 125.00 PASS
DL.1 4 4 2 16.5 4000 125.00 PASS 5 N/A10
DL.2 4 4 2 16.5 4000 125.00 PASS
DL.1 2 2 2 16.5 4000 125.00 PASS 5 N/A10
DL.2 2 2 2 16.5 4000 125.00 PASS
DL.1 2 4 4 16.5 4000 125.00 PASS 5 N/A10
DL.2 2 4 4 16.5 4000 125.00 PASS
DL.1 8 8 1 17.16 5200 130.00 PASS 5 N/A10
DL.2 8 8 1 17.16 5200 130.00 PASS
DL.1 6 6 1 16.5 4000 125.00 PASS 5 N/A10
DL.2 6 6 1 16.5 4000 125.00 PASS
10 The Timestamp feature of ADC12DJ5200RF is not supported when decimation or JESD testpattern (ramp/short/long transport test pattern) is enabled in the device and hence latency is not measured for those modes.
Level Two Title