AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

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ID 683185
Date 6/09/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. ADC12DJxx00RF EVM Software and JESD204C Example Design Setup 1.4. Hardware Checkout Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices 1.9. Appendix
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment 1.4.1.2. Extended Multiblock Alignment
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

1.2. Hardware Setup

An Intel® Stratix® 10 TX SI Development Kit (Production Rev B Edition) is used with the TI ADC12DJ5200RF daughter card module installed to the FMC+ connector of the development board.

  • The ADC12DJ5200RF EVM derives power from 12 V power adaptor.
  • The ADC12DJ5200RF EVM is configured in the onboard clocking option (refer to the Onboard Clocking Option section of the ADC12DJ5200RF Evaluation Module User’s Guide) and all the required clocks are generated by the ADC12DJ5200RF EVM and no external clock signals are required.
  • The LMK61E2 programmable oscillator generates the reference frequency. The LMK00304 clock buffer make two copies of the reference signal and sends one copy to the LMX2594 frequency synthesizer to generate the sampling clock for the ADC.
  • The LMK04828 clock generator uses the second copy in a clock distribution mode to provide the JESD204C Intel® FPGA IP core PLL reference clock, and the E-tile transceiver reference clock through the FMC+ connector.
  • For Subclass 1, the LMK04828 clock generator generates the SYSREF signal for the JESD204C Intel® FPGA IP and the LMX2594 generates the SYSREF signal for the ADC12DJ5200RF device.
Note: Intel® recommends the SYSREF to be provided by the clock generator that sources the JESD204C Intel® FPGA IP device clock and sampling clock to ADC.
Figure 1. Hardware Setup

The following system level diagram shows how the different modules connect in this design.

Figure 2. System Diagram

In this setup, where LMF = 828, the data rate of transceiver lanes is 17.16 Gbps.

The LMK61E2 generated 260 MHz reference clock to the LMK00304. The LMK04828 takes the 260 MHz reference clock from the LMK00304 and distributes 260 MHz to JESD204C Intel® FPGA IP device clock and E-tile transceiver reference clock through the FMC+ connector.

The LMK04828 also divides the 260 MHz reference clock to 8.125 MHz to provide a periodic SYSREF signal to the JESD204C Intel® FPGA IP and the SYSREFREQ pin of the LMX2594.

The LMX2594 takes the 260 MHz reference clock from LMK00304 and generates 5200 MHz sampling clock to ADC12DJ5200RF device.

The LMX2594 is configured in SYSREF REPEATER mode to align the generated sampling clock and SYSREF from LMK04828 through SYSREFREQ pin. It provides a SYSREF of 8.125 MHz to ADC12DJ5200RF device.

The JESD204C Intel® FPGA IP is instantiated in duplex mode but only the receiver path is used. For FCLK_MULP = 1, WIDTH_MULP = 2, and S = 1, the core PLL generates 130 MHz frame clock and link clock.

The TMSTP signal from the FPGA to ADC12DJ5200RF is for deterministic latency measurement.

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